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Message-ID: <7bf8bffe-267b-6c66-86c9-40017d3ca4c2@siemens.com>
Date: Thu, 30 Apr 2020 14:59:50 +0200
From: Jan Kiszka <jan.kiszka@...mens.com>
To: Srivatsa Vaddagiri <vatsa@...eaurora.org>,
Will Deacon <will@...nel.org>
Cc: konrad.wilk@...cle.com, mst@...hat.com, jasowang@...hat.com,
stefano.stabellini@...inx.com, iommu@...ts.linux-foundation.org,
virtualization@...ts.linux-foundation.org,
virtio-dev@...ts.oasis-open.org, tsoni@...eaurora.org,
pratikp@...eaurora.org, christoffer.dall@....com,
alex.bennee@...aro.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC/PATCH 1/1] virtio: Introduce MMIO ops
On 30.04.20 13:11, Srivatsa Vaddagiri wrote:
> * Will Deacon <will@...nel.org> [2020-04-30 11:41:50]:
>
>> On Thu, Apr 30, 2020 at 04:04:46PM +0530, Srivatsa Vaddagiri wrote:
>>> If CONFIG_VIRTIO_MMIO_OPS is defined, then I expect this to be unconditionally
>>> set to 'magic_qcom_ops' that uses hypervisor-supported interface for IO (for
>>> example: message_queue_send() and message_queue_recevie() hypercalls).
>>
>> Hmm, but then how would such a kernel work as a guest under all the
>> spec-compliant hypervisors out there?
>
> Ok I see your point and yes for better binary compatibility, the ops have to be
> set based on runtime detection of hypervisor capabilities.
>
>>> Ok. I guess the other option is to standardize on a new virtio transport (like
>>> ivshmem2-virtio)?
>>
>> I haven't looked at that, but I suppose it depends on what your hypervisor
>> folks are willing to accomodate.
>
> I believe ivshmem2_virtio requires hypervisor to support PCI device emulation
> (for life-cycle management of VMs), which our hypervisor may not support. A
> simple shared memory and doorbell or message-queue based transport will work for
> us.
As written in our private conversation, a mapping of the ivshmem2 device
discovery to platform mechanism (device tree etc.) and maybe even the
register access for doorbell and life-cycle management to something
hypercall-like would be imaginable. What would count more from virtio
perspective is a common mapping on a shared memory transport.
That said, I also warned about all the features that PCI already defined
(such as message-based interrupts) which you may have to add when going
a different way for the shared memory device.
Jan
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Corporate Competence Center Embedded Linux
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