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Date: Fri, 1 May 2020 08:39:02 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: peterz@...radead.org, mingo@...hat.com,
linux-kernel@...r.kernel.org
Cc: ak@...ux.intel.com
Subject: Re: [PATCH V2] perf/x86/intel/uncore: Add Comet Lake support
Hi Peter,
Could you please take a look the patch, and apply the patch if it's OK?
Thanks,
Kan
On 4/2/2020 3:52 PM, kan.liang@...ux.intel.com wrote:
> From: Kan Liang <kan.liang@...ux.intel.com>
>
> The uncore subsystem on Comet Lake is similar to Sky Lake.
> The only difference is the new PCI IDs for IMC.
>
> Share the perf code with Sky Lake.
> Add new PCI IDs in the table.
>
> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
> ---
>
> Changes since V1:
> - Rebase on top of tip.git perf/core branch
> commit 629b3df7ecb0 ("Merge branch 'x86/cpu' into perf/core, to resolve conflict")
>
> arch/x86/events/intel/uncore.c | 2 ++
> arch/x86/events/intel/uncore_snb.c | 66 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
> index cf76d66..b9c2876 100644
> --- a/arch/x86/events/intel/uncore.c
> +++ b/arch/x86/events/intel/uncore.c
> @@ -1514,6 +1514,8 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
> X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &skx_uncore_init),
> X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &skl_uncore_init),
> X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &skl_uncore_init),
> + X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &skl_uncore_init),
> + X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &skl_uncore_init),
> X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_uncore_init),
> X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &icl_uncore_init),
> X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_uncore_init),
> diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
> index 3de1065..5c40367 100644
> --- a/arch/x86/events/intel/uncore_snb.c
> +++ b/arch/x86/events/intel/uncore_snb.c
> @@ -42,6 +42,17 @@
> #define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC 0x3ed0
> #define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC 0x3e34
> #define PCI_DEVICE_ID_INTEL_WHL_UD_IMC 0x3e35
> +#define PCI_DEVICE_ID_INTEL_CML_H1_IMC 0x9b44
> +#define PCI_DEVICE_ID_INTEL_CML_H2_IMC 0x9b54
> +#define PCI_DEVICE_ID_INTEL_CML_H3_IMC 0x9b64
> +#define PCI_DEVICE_ID_INTEL_CML_U1_IMC 0x9b51
> +#define PCI_DEVICE_ID_INTEL_CML_U2_IMC 0x9b61
> +#define PCI_DEVICE_ID_INTEL_CML_U3_IMC 0x9b71
> +#define PCI_DEVICE_ID_INTEL_CML_S1_IMC 0x9b33
> +#define PCI_DEVICE_ID_INTEL_CML_S2_IMC 0x9b43
> +#define PCI_DEVICE_ID_INTEL_CML_S3_IMC 0x9b53
> +#define PCI_DEVICE_ID_INTEL_CML_S4_IMC 0x9b63
> +#define PCI_DEVICE_ID_INTEL_CML_S5_IMC 0x9b73
> #define PCI_DEVICE_ID_INTEL_ICL_U_IMC 0x8a02
> #define PCI_DEVICE_ID_INTEL_ICL_U2_IMC 0x8a12
> #define PCI_DEVICE_ID_INTEL_TGL_U1_IMC 0x9a02
> @@ -771,6 +782,50 @@ static const struct pci_device_id skl_uncore_pci_ids[] = {
> PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UD_IMC),
> .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H1_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H2_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_H3_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U1_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U2_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_U3_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S1_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S2_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S3_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S4_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> + { /* IMC */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_S5_IMC),
> + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> + },
> { /* end: all zeroes */ },
> };
>
> @@ -863,6 +918,17 @@ static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
> IMC_DEV(WHL_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
> IMC_DEV(WHL_4_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
> IMC_DEV(WHL_UD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Dual Core */
> + IMC_DEV(CML_H1_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_H2_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_H3_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_U1_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_U2_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_U3_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_S1_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_S2_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_S3_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_S4_IMC, &skl_uncore_pci_driver),
> + IMC_DEV(CML_S5_IMC, &skl_uncore_pci_driver),
> IMC_DEV(ICL_U_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
> IMC_DEV(ICL_U2_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
> { /* end marker */ }
>
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