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Date:   Sun, 3 May 2020 22:35:42 +0100
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     anshuman.khandual@....com, linux-arm-kernel@...ts.infradead.org
Cc:     catalin.marinas@....com, will@...nel.org, maz@...nel.org,
        mark.rutland@....com, james.morse@....com,
        kvmarm@...ts.cs.columbia.edu, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V3 05/16] arm64/cpufeature: Introduce ID_DFR1 CPU register

On 05/02/2020 02:33 PM, Anshuman Khandual wrote:
> This adds basic building blocks required for ID_DFR1 CPU register which
> provides top level information about the debug system in AArch32 state.
> This is added per ARM DDI 0487F.a specification.
> 
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will@...nel.org>
> Cc: Marc Zyngier <maz@...nel.org>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: James Morse <james.morse@....com>
> Cc: Suzuki K Poulose <suzuki.poulose@....com>
> Cc: kvmarm@...ts.cs.columbia.edu
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> 
> Suggested-by: Will Deacon <will@...nel.org>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
> ---
>   arch/arm64/include/asm/cpu.h    |  1 +
>   arch/arm64/include/asm/sysreg.h |  3 +++
>   arch/arm64/kernel/cpufeature.c  | 10 ++++++++++
>   arch/arm64/kernel/cpuinfo.c     |  1 +
>   arch/arm64/kvm/sys_regs.c       |  2 +-
>   5 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index 464e828a994d..d9a78bdec409 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -33,6 +33,7 @@ struct cpuinfo_arm64 {
>   	u64		reg_id_aa64zfr0;
>   
>   	u32		reg_id_dfr0;
> +	u32		reg_id_dfr1;
>   	u32		reg_id_isar0;
>   	u32		reg_id_isar1;
>   	u32		reg_id_isar2;
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c977449e02db..2e1e922e1409 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -154,6 +154,7 @@
>   #define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
>   #define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
>   #define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)
> +#define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)
>   
>   #define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)
>   #define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)
> @@ -763,6 +764,8 @@
>   #define ID_ISAR4_WITHSHIFTS_SHIFT	4
>   #define ID_ISAR4_UNPRIV_SHIFT		0
>   
> +#define ID_DFR1_MTPMU_SHIFT		0
> +
>   #define ID_ISAR0_DIVIDE_SHIFT		24
>   #define ID_ISAR0_DEBUG_SHIFT		20
>   #define ID_ISAR0_COPROC_SHIFT		16
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index a8247bf92959..2ce952d9668d 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -451,6 +451,11 @@ static const struct arm64_ftr_bits ftr_id_dfr0[] = {
>   	ARM64_FTR_END,
>   };
>   
> +static const struct arm64_ftr_bits ftr_id_dfr1[] = {
> +	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),


> -	ID_UNALLOCATED(3,5),
> +	ID_SANITISED(ID_DFR1_EL1),
>   	ID_UNALLOCATED(3,6),
>   	ID_UNALLOCATED(3,7),
>   

IIUC, we should not expose the MTPMU to the KVM guests. Either we could 
drop this entire patch, or we should emulate the MTPMU to 0 in KVM.

Suzuki

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