[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20200504201220.GA21544@qmqm.qmqm.pl>
Date: Mon, 4 May 2020 22:12:21 +0200
From: Michał Mirosław <mirq-linux@...e.qmqm.pl>
To: Alexandre Belloni <alexandre.belloni@...tlin.com>
Cc: Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Ludovic Desroches <ludovic.desroches@...rochip.com>,
Nicolas Ferre <nicolas.ferre@...rochip.com>,
Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v4 3/3] clk: at91: allow setting all PMC clock parents
via DT
On Mon, May 04, 2020 at 10:04:31PM +0200, Alexandre Belloni wrote:
> Hi,
>
> On 03/05/2020 19:19:26+0200, Michał Mirosław wrote:
> > diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
> > index c3f4aa6a2d29..adcf608b41fa 100644
> > --- a/include/dt-bindings/clock/at91.h
> > +++ b/include/dt-bindings/clock/at91.h
> > @@ -21,6 +21,9 @@
> > #define PMC_MCK2 4
> > #define PMC_I2S0_MUX 5
> > #define PMC_I2S1_MUX 6
> > +#define PMC_PLLACK 7
> > +#define PMC_PLLBCK 8
> > +#define PMC_AUDIOPLLCK 8 /* SAMA5D2-only, no PLLB there */
> Just use 9 here because we can't know for sure that a future SoC won't
> have both a PLLB and audio PLL.
Ok. I assumed that PLLB is only in old generations. Fix coming shortly.
Best Regrads,
Michał Mirosław
Powered by blists - more mailing lists