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Message-ID: <CAMuHMdW=njc2Vvu+7WHgikWOMtWCWTMmxeYLWLP0Z1TyStiaFg@mail.gmail.com>
Date: Mon, 4 May 2020 12:28:39 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Cc: Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Vinod Koul <vkoul@...nel.org>,
Ulf Hansson <ulf.hansson@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
dmaengine <dmaengine@...r.kernel.org>,
Linux MMC List <linux-mmc@...r.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
"open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
Prabhakar <prabhakar.csengg@...il.com>
Subject: Re: [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree
Hi Prabhakar,
On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC,
> CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer
> and the required clock descriptions.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...renesas.com>
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7742.dtsi
> + icram2: sram@...00000 {
> + compatible = "mmio-sram";
> + reg = <0 0xe6300000 0 0x40000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0xe6300000 0x40000>;
> + };
> +
> + scifa2: serial@...60000 {
> + compatible = "renesas,scifa-r8a7742",
> + "renesas,rcar-gen2-scifa", "renesas,scifa";
> + reg = <0 0xe6c60000 0 0x40>;
> + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 202>;
> + clock-names = "fck";
> + dmas = <&dmac0 0x27>, <&dmac0 0x28>,
> + <&dmac1 0x27>, <&dmac1 0x28>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> + resets = <&cpg 202>;
> + status = "disabled";
> + };
> +
> + mmcif1: mmc@...20000 {
> + compatible = "renesas,mmcif-r8a7742",
> + "renesas,sh-mmcif";
> + reg = <0 0xee220000 0 0x80>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 305>;
> + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
> + <&dmac1 0xe1>, <&dmac1 0xe2>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> + resets = <&cpg 305>;
> + reg-io-width = <4>;
> + status = "disabled";
> + max-frequency = <97500000>;
> + };
> +
> + dmac0: dma-controller@...00000 {
> + compatible = "renesas,dmac-r8a7742",
> + "renesas,rcar-dmac";
> + reg = <0 0xe6700000 0 0x20000>;
> + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14";
> + clocks = <&cpg CPG_MOD 219>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> + resets = <&cpg 219>;
> + #dma-cells = <1>;
> + dma-channels = <15>;
> + };
> +
> + dmac1: dma-controller@...20000 {
> + compatible = "renesas,dmac-r8a7742",
> + "renesas,rcar-dmac";
> + reg = <0 0xe6720000 0 0x20000>;
> + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14";
> + clocks = <&cpg CPG_MOD 218>;
> + clock-names = "fck";
> + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> + resets = <&cpg 218>;
> + #dma-cells = <1>;
> + dma-channels = <15>;
> + };
To preserve sort order, the DMAC nodes should be moved up.
No need to resend, will fix up while applying.
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-devel for v5.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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