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Date: Mon, 4 May 2020 09:54:35 +0800 From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@...ux.intel.com> To: Boris Brezillon <boris.brezillon@...labora.com> Cc: qi-ming.wu@...el.com, linux-kernel@...r.kernel.org, linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org, cheol.yong.kim@...el.com, hauke.mehrtens@...el.com, anders.roxell@...aro.org, vigneshr@...com, arnd@...db.de, richard@....at, brendanhiggins@...gle.com, linux-mips@...r.kernel.org, robh+dt@...nel.org, miquel.raynal@...tlin.com, tglx@...utronix.de, masonccyang@...c.com.tw, andriy.shevchenko@...el.com Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Hi Boris, Thank you very much for the review comments and giving inputs... On 30/4/2020 8:36 pm, Boris Brezillon wrote: > On Thu, 30 Apr 2020 17:07:03 +0800 > "Ramuthevar, Vadivel MuruganX" > <vadivel.muruganx.ramuthevar@...ux.intel.com> wrote: > >>>>> The question is, is it the same value we have in nand_pa or it is >>>>> different? >>>>> >>>> Different address which is 0xE1400000 NAND_BASE_PHY address. >>> >>> Then why didn't you tell me they didn't match when I suggested to pass >> >> sorry, because you keep asking nand_pa after that only I realized that. >> >>> nand_pa? So now the question is, what does this address represent? >> >> EBU-MODULE >> _________ _______________________ >> | | | |NAND CTRL | >> | FPI BUS |==>| CS0(0x174) | 0xE100 ( 0xE14/0xE1C) NAND_PHY_BASE >> |_________| |_CS1(0x17C)_|__________ | >> >> EBU_CONRTROLLER_BASE : 0xE0F0_0000 >> HSNAND_BASE: 0xE100_0000 >> NAND_CS0: 0xE140_0000 >> NAND_CS1: 0xE1C0_0000 >> >> MEM_REGION_BASE_CS0: 0x17400 (internal to ebu controller ) >> MEM_REGION_BASE_CS1: 0x17C00 >> > > Hm, I wonder if we shouldn't use a 'ranges' property to describe this > address translation. Something like > > ebu@xxx { > ranges = <0x17400000 0xe1400000 0x1000>, > <0x17c00000 0xe1c00000 0x1000>; > reg = <0x17400000>, <0x17c00000>; > reg-names = "cs-0", "cs-1"; > } > > The translated address (0xE1X00000) will be available in res->start, > and the non-translated one (0x17X00000) can be retrieved with > of_get_address(). All you'd have to do then would be calculate the > mask: > > mask = (translated_address & original_address) >> 22; > num_comp_bits = fls(mask); > WARN_ON(mask != GENMASK(num_comp_bits - 1, 0)); > > Which allows you to properly set the ADDR_SEL() register without > relying on some hardcoded values: > > writel(original_address | EBU_ADDR_SEL_REGEN | > EBU_ADDR_COMP_BITS(num_comp_bits), > ebu_host->ebu + EBU_ADDR_SEL(csid)); > > That's quite important if we want to merge the xway NAND driver with > this one. Thanks! , for the optimized and made it generic way, will update in the next patch-set. Regards Vadivel >
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