linux-kernel - Re: [PATCH 1/3] pci: Add Designated Vendor Specific Capability

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 5 May 2020 11:49:51 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     "David E. Box" <david.e.box@...ux.intel.com>
Cc:     Bjorn Helgaas <bhelgaas@...gle.com>,
        Andy Shevchenko <andy@...radead.org>,
        alexander.h.duyck@...el.com,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-pci@...r.kernel.org
Subject: Re: [PATCH 1/3] pci: Add Designated Vendor Specific Capability

On Tue, May 5, 2020 at 4:32 AM David E. Box <david.e.box@...ux.intel.com> wrote:
>
> Add pcie dvsec extended capability id along with helper macros to

pcie -> PCIe

dvsec -> DVSEC (but here I'm not sure, what's official abbreviation for this?)

> retrieve information from the headers.



> https://members.pcisig.com/wg/PCI-SIG/document/12335

Perhaps

DocLink: ...

(as a tag)

>
> Signed-off-by: David E. Box <david.e.box@...ux.intel.com>
> ---
>  include/uapi/linux/pci_regs.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index f9701410d3b5..c96f08d1e711 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -720,6 +720,7 @@
>  #define PCI_EXT_CAP_ID_DPC     0x1D    /* Downstream Port Containment */
>  #define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
>  #define PCI_EXT_CAP_ID_PTM     0x1F    /* Precision Time Measurement */
> +#define PCI_EXT_CAP_ID_DVSEC   0x23    /* Desinated Vendor-Specific */
>  #define PCI_EXT_CAP_ID_DLF     0x25    /* Data Link Feature */
>  #define PCI_EXT_CAP_ID_PL_16GT 0x26    /* Physical Layer 16.0 GT/s */
>  #define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_PL_16GT
> @@ -1062,6 +1063,10 @@
>  #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE        0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
>  #define PCI_L1SS_CTL2          0x0c    /* Control 2 Register */
>
> +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
> +#define PCI_DVSEC_HEADER1              0x4 /* Vendor-Specific Header1 */
> +#define PCI_DVSEC_HEADER2              0x8 /* Vendor-Specific Header2 */
> +
>  /* Data Link Feature */
>  #define PCI_DLF_CAP            0x04    /* Capabilities Register */
>  #define  PCI_DLF_EXCHANGE_ENABLE       0x80000000  /* Data Link Feature Exchange Enable */
> --
> 2.20.1
>


-- 
With Best Regards,
Andy Shevchenko