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Date:   Tue, 5 May 2020 11:24:39 +0000
From:   Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Alan Mikhak <alan.mikhak@...ive.com>,
        "jingoohan1@...il.com" <jingoohan1@...il.com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "amurray@...goodpenguin.co.uk" <amurray@...goodpenguin.co.uk>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "kishon@...com" <kishon@...com>,
        "paul.walmsley@...ive.com" <paul.walmsley@...ive.com>
Subject: RE: [PATCH] PCI: dwc: Program outbound ATU upper limit register

Hi Lorenzo,

On Tue, May 5, 2020 at 11:29:33, Lorenzo Pieralisi 
<lorenzo.pieralisi@....com> wrote:

> On Wed, Apr 01, 2020 at 04:58:13PM -0700, Alan Mikhak wrote:
> > From: Alan Mikhak <alan.mikhak@...ive.com>
> > 
> > Function dw_pcie_prog_outbound_atu_unroll() does not program the upper
> > 32-bit ATU limit register. Since ATU programming functions limit the
> > size of the translated region to 4GB by using a u32 size parameter,
> > these issues may combine into undefined behavior for resource sizes
> > with non-zero upper 32-bits.
> > 
> > For example, a 128GB address space starting at physical CPU address of
> > 0x2000000000 with size of 0x2000000000 needs the following values
> > programmed into the lower and upper 32-bit limit registers:
> >  0x3fffffff in the upper 32-bit limit register
> >  0xffffffff in the lower 32-bit limit register
> > 
> > Currently, only the lower 32-bit limit register is programmed with a
> > value of 0xffffffff but the upper 32-bit limit register is not being
> > programmed. As a result, the upper 32-bit limit register remains at its
> > default value after reset of 0x0.
> > 
> > These issues may combine to produce undefined behavior since the ATU
> > limit address may be lower than the ATU base address. Programming the
> > upper ATU limit address register prevents such undefined behavior despite
> > the region size getting truncated due to the 32-bit size limit.
> > 
> > Signed-off-by: Alan Mikhak <alan.mikhak@...ive.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware.c | 7 +++++--
> >  drivers/pci/controller/dwc/pcie-designware.h | 3 ++-
> >  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> I would appreciate some feedback and possibly and ACK from DWC
> maintainers. Should this go to stable kernels ? It seems so,
> let me know if we want to add a stable tag.
> 
> I will merge it, along with:
> 
> https://urldefense.com/v3/__https://patchwork.kernel.org/patch/11468465/__;!!A4F2R9G_pg!NoymSJCWmOx51jB7LdQQAbXFin14nfuVIQNQxROnskLmmGkzFeNOrf8nFWX_-KgsgO87N9M$ 
> 
> Lorenzo

Sorry for the delay. I just gave the ACK to that patch. For me, it makes 
sense to me to send it along with the patch that you just referred to the 
stable kernels.

-Gustavo

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