linux-kernel - [PATCH v2 3/9] ARM: dts: r8a7742: Add IRQC support

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Message-Id: <1588794695-27852-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date:   Wed,  6 May 2020 20:51:29 +0100
From:   Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
To:     Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <maz@...nel.org>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc:     linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org,
        linux-gpio@...r.kernel.org, linux-serial@...r.kernel.org,
        Prabhakar <prabhakar.csengg@...il.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH v2 3/9] ARM: dts: r8a7742: Add IRQC support

Describe the IRQC interrupt controller in the r8a7742 device tree.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Acked-by: Marc Zyngier <maz@...nel.org>
---
v1->v2:
* No change
---

 arch/arm/boot/dts/r8a7742.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 3d3d95678496..06a4241bafd8 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -226,6 +226,20 @@
 			#power-domain-cells = <1>;
 		};
 
+		irqc: interrupt-controller@...c0000 {
+			compatible = "renesas,irqc-r8a7742", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+			resets = <&cpg 407>;
+		};
+
 		icram0: sram@...a0000 {
 			compatible = "mmio-sram";
 			reg = <0 0xe63a0000 0 0x12000>;
-- 
2.17.1