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Date:   Thu, 7 May 2020 22:25:58 +0200
From:   Paul Kocialkowski <paul.kocialkowski@...tlin.com>
To:     Johan Jonker <jbx6244@...il.com>
Cc:     devicetree@...r.kernel.org, ezequiel@...labora.com,
        hansverk@...co.com, heiko@...ech.de,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        mchehab@...nel.org, robh+dt@...nel.org,
        thomas.petazzoni@...tlin.com
Subject: Re: [PATCH v3 2/4] arm64: dts: rockchip: Add RGA support to the PX30

Hi,

On Fri 01 May 20, 00:05, Johan Jonker wrote:
> Hi Paul,
> 
> > The PX30 features a RGA block: add the necessary node to support it.
> > 
> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@...tlin.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/px30.dtsi | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > index f809dd6d5dc3..3de70aa4f1ce 100644
> > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > @@ -1102,6 +1102,17 @@ vopl_mmu: iommu@...70f00 {
> >  		status = "disabled";
> >  	};
> >  
> > +	rga: rga@...80000 {
> > +		compatible = "rockchip,px30-rga", "rockchip,rk3288-rga";
> > +		reg = <0x0 0xff480000 0x0 0x10000>;
> > +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH 0>;
> > +		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
> > +		clock-names = "aclk", "hclk", "sclk";
> 
> > +		resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
> > +		reset-names = "core", "axi", "ahb";
> > +		power-domains = <&power PX30_PD_VO>;
> 
> sort
> 
> 		power-domains = <&power PX30_PD_VO>;
> 		resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
> 		reset-names = "core", "axi", "ahb";

What's the rationale behind this (besides alphabetic sorting, which I don't
believe is a rule for dt properties)? Some nodes above in the file have it in
the same order that I do, and I like to see clocks followed by resets.

Cheers,

Paul

> 
> 
> > +	};
> > +
> >  	qos_gmac: qos@...18000 {
> >  		compatible = "syscon";
> >  		reg = <0x0 0xff518000 0x0 0x20>;
> > -- 
> > 2.26.0
> 

-- 
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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