Message-ID: <20200508093621.31619-2-Sergey.Semin@baikalelectronics.ru>
Date:   Fri, 8 May 2020 12:36:20 +0300
From:   Serge Semin <Sergey.Semin@...kalelectronics.ru>
To:     Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>
CC:     Serge Semin <Sergey.Semin@...kalelectronics.ru>,
        Serge Semin <fancer.lancer@...il.com>,
        Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        John Garry <john.garry@...wei.com>,
        Chuanhong Guo <gch981213@...il.com>,
        Tomer Maimon <tmaimon77@...il.com>,
        Lee Jones <lee.jones@...aro.org>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        Arnd Bergmann <arnd@...db.de>, <linux-mips@...r.kernel.org>,
        <linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: [PATCH 1/2] dt-bindings: spi: Add Baikal-T1 System Boot SPI Controller binding

Baikal-T1 Boot SPI is a part of the SoC System Controller and is
responsible for the system bootup from an external SPI flash. It's a DW
APB SSI-based SPI-controller with no interrupts, no DMA, with just one
native chip-select available and a single reference clock. Since Baikal-T1
SoC is normally booted up from an external SPI flash this SPI controller
in most of the cases is supposed to be connected to a single SPI-nor
flash. Additionally in order to provide a transparent from CPU point of
view initial code execution procedure the system designers created an IP
block which physically maps the SPI flash found at CS0 to a memory region.

Co-developed-by: Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc: Paul Burton <paulburton@...nel.org>
Cc: Ralf Baechle <ralf@...ux-mips.org>
Cc: John Garry <john.garry@...wei.com>
Cc: Chuanhong Guo <gch981213@...il.com>
Cc: Tomer Maimon <tmaimon77@...il.com>
Cc: Lee Jones <lee.jones@...aro.org>
Cc: Miquel Raynal <miquel.raynal@...tlin.com>
Cc: Arnd Bergmann <arnd@...db.de>
Cc: linux-mips@...r.kernel.org
Cc: linux-spi@...r.kernel.org
---
 .../bindings/spi/baikal,bt1-sys-ssi.yaml      | 100 ++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml

diff --git a/Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml b/Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml
new file mode 100644
index 000000000000..d9d3257d78f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/baikal,bt1-sys-ssi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 System Boot SSI Controller
+
+description: |
+  Baikal-T1 System Controller includes a Boot SPI Controller, which is
+  responsible for loading chip bootup code from an external SPI flash. In order
+  to do this transparently from CPU point of view there is a dedicated IP block
+  mapping the 16MB flash to a dedicated MMIO range. The controller is based on
+  the DW APB SSI IP-core but equipped with very limited resources: no IRQ,
+  no DMA, a single native CS being necessarily connected to a 16MB SPI flash
+  (otherwise the system won't bootup from the flash), internal Tx/Rx FIFO of
+  just 8 bytes depth. Access to DW APB SSI controller registers is mutually
+  exclusive from normal MMIO interface and from physically mapped SPI Flash
+  memory. So either one or another way of using the controller functionality
+  can be enabled at a time.
+
+maintainers:
+  - Serge Semin <fancer.lancer@...il.com>
+
+allOf:
+  - $ref: spi-controller.yaml#
+
+properties:
+  compatible:
+    const: baikal,bt1-sys-ssi
+
+  reg:
+    items:
+      - description: Baikal-T1 Boot Controller configuration registers
+      - description: Physically mapped SPI flash ROM found at CS0
+
+  reg-names:
+    items:
+      - const: config
+      - const: map
+
+  clocks:
+    description: SPI Controller reference clock source
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ssi_clk
+
+  num-cs:
+    const: 1
+
+patternProperties:
+  "^.*@[0-9a-f]+":
+    type: object
+    properties:
+      reg:
+        minimum: 0
+        maximum: 0
+
+      spi-rx-bus-width:
+        const: 1
+
+      spi-tx-bus-width:
+        const: 1
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - "#address-cells"
+  - "#size-cells"
+  - clocks
+
+examples:
+  - |
+    spi@...40000 {
+      compatible = "baikal,bt1-sys-ssi";
+      reg = <0x1f040000 0x1000>,
+            <0x1c000000 0x1000000>;
+      reg-names = "config", "map";
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      clocks = <&ccu_sys>;
+      clock-names = "ssi_clk";
+
+      boot_flash: flash@0 {
+        compatible = "jedec,spi-nor";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0>;
+
+        spi-max-frequency = <25000000>;
+      };
+    };
+...
-- 
2.25.1

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