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Message-ID: <20200509083654.5178-4-chao.hao@mediatek.com>
Date: Sat, 9 May 2020 16:36:50 +0800
From: Chao Hao <chao.hao@...iatek.com>
To: Joerg Roedel <joro@...tes.org>, Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
CC: <iommu@...ts.linux-foundation.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>, <wsd_upstream@...iatek.com>,
Chao Hao <chao.hao@...iatek.com>,
Yong Wu <yong.wu@...iatek.com>, FY Yang <fy.yang@...iatek.com>,
Jun Yan <jun.yan@...iatek.com>
Subject: [PATCH v3 3/7] iommu/mediatek: Disable STANDARD_AXI_MODE in MISC_CTRL
In order to improve performance, we always disable STANDARD_AXI_MODE in
MISC_CTRL.
Signed-off-by: Chao Hao <chao.hao@...iatek.com>
---
drivers/iommu/mtk_iommu.c | 8 +++++++-
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index e7e7c7695ed1..9ede327a418d 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -42,6 +42,8 @@
#define F_INVLD_EN1 BIT(1)
#define REG_MMU_MISC_CTRL 0x048
+#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19))
+
#define REG_MMU_DCM_DIS 0x050
#define REG_MMU_CTRL_REG 0x110
@@ -585,7 +587,11 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
- if (data->plat_data->reset_axi) {
+ if (data->plat_data->has_misc_ctrl) {
+ regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+ regval &= ~F_MMU_STANDARD_AXI_MODE_BIT;
+ writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
+ } else if (data->plat_data->reset_axi) {
/* The register is called STANDARD_AXI_MODE in this case */
writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 1b6ea839b92c..d711ac630037 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -40,6 +40,7 @@ struct mtk_iommu_plat_data {
/* HW will use the EMI clock if there isn't the "bclk". */
bool has_bclk;
+ bool has_misc_ctrl;
bool has_vld_pa_rng;
bool reset_axi;
unsigned char larbid_remap[MTK_LARB_NR_MAX];
--
2.18.0
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