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Date:   Sat, 9 May 2020 17:24:03 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Hui Song <hui.song_1@....com>
Cc:     u-boot@...ux.nxdi.nxp.com, jiafei.pan@....com,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-gpio@...r.kernel.org
Subject: Re: [PATCH v1 1/3] gpio: mpc8xxx: support fsl-layerscape platform.

On Sat, May 09, 2020 at 06:39:54PM +0800, Hui Song wrote:
> From: "hui.song" <hui.song_1@....com>
> 
> Make the MPC8XXX gpio driver to support the fsl-layerscape.
> 
> Signed-off-by: hui.song <hui.song_1@....com>
> ---
>  drivers/gpio/mpc8xxx_gpio.c | 59 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
> 
> diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
> index 1dfd22522c..466f5f50cf 100644
> --- a/drivers/gpio/mpc8xxx_gpio.c
> +++ b/drivers/gpio/mpc8xxx_gpio.c
> @@ -12,6 +12,8 @@
>  #include <dm.h>
>  #include <mapmem.h>
>  #include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <dm/of_access.h>
>  
>  struct ccsr_gpio {
>  	u32	gpdir;
> @@ -20,6 +22,7 @@ struct ccsr_gpio {
>  	u32	gpier;
>  	u32	gpimr;
>  	u32	gpicr;
> +	u32	gpibe;
>  };
>  
>  struct mpc8xxx_gpio_data {
> @@ -49,31 +52,51 @@ inline u32 gpio_mask(uint gpio)
>  
>  static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
>  {
> +#if CONFIG_ARM
> +	return in_le32(&base->gpdat) & mask;
> +#else
>  	return in_be32(&base->gpdat) & mask;
> +#endif
>  }

Hi Hui

Did the hardware engineers really change the endinness of the
register? Forget about the CPU here, did the register change
endinness? In general, you should not need to use #if like this, so
long as the register itself is still the same. There are functions
which will do the correct thing depending on if the CPU is big or
little endian.

> @@ -147,13 +183,29 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
>  {
>  	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
>  	fdt_addr_t addr;
> +	u32 i;
> +#if CONFIG_ARM
> +	u32 reg[4];
> +
> +	dev_read_u32_array(dev, "reg", reg, 4);
> +#else
>  	u32 reg[2];
>  
>  	dev_read_u32_array(dev, "reg", reg, 2);
> +#endif
> +
> +#if CONFIG_ARM
> +	for (i = 0; i < 2; i++)
> +		reg[i] = be32_to_cpu(reg[i]);
> +#endif
>  	addr = dev_translate_address(dev, reg);
>  
>  	plat->addr = addr;
> +#if CONFIG_ARM
> +	plat->size = reg[3];
> +#else
>  	plat->size = reg[1];
> +#endif
>  	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);

So you are extending the DT binding. You need to document this. And it
should really have a different compatible string, since the binding is
not compatible between the two variants.
>  
>  	return 0;
> @@ -187,6 +239,7 @@ static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
>  static int mpc8xxx_gpio_probe(struct udevice *dev)
>  {
>  	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +	struct device_node const  *np = dev->node.np;
>  	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
>  	char name[32], *str;
>  
> @@ -198,6 +251,12 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
>  	if (!str)
>  		return -ENOMEM;
>  
> +	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
> +		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
> +
> +		out_be32(gpibe, 0xffffffff);

That is an odd way to determine the address of a register.

     Andrew

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