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Date:   Tue, 12 May 2020 14:10:41 -0000
From:   "tip-bot2 for Uros Bizjak" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Uros Bizjak <ubizjak@...il.com>, Borislav Petkov <bp@...e.de>,
        "H. Peter Anvin (Intel)" <hpa@...or.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        x86 <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: [tip: x86/cpu] x86/cpu: Use INVPCID mnemonic in invpcid.h

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     7e32a9dac9926241d56851e1517c9391d39fb48e
Gitweb:        https://git.kernel.org/tip/7e32a9dac9926241d56851e1517c9391d39fb48e
Author:        Uros Bizjak <ubizjak@...il.com>
AuthorDate:    Fri, 08 May 2020 11:22:47 +02:00
Committer:     Borislav Petkov <bp@...e.de>
CommitterDate: Tue, 12 May 2020 16:05:30 +02:00

x86/cpu: Use INVPCID mnemonic in invpcid.h

The current minimum required version of binutils is 2.23, which supports
the INVPCID instruction mnemonic. Replace the byte-wise specification of
INVPCID with the proper mnemonic.

 [ bp: Add symbolic operand names for increased readability and flip
   their order like the insn expects them for the AT&T syntax. ]

Signed-off-by: Uros Bizjak <ubizjak@...il.com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Reviewed-by: H. Peter Anvin (Intel) <hpa@...or.com>
Acked-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/20200508092247.132147-1-ubizjak@gmail.com

Signed-off-by: Borislav Petkov <bp@...e.de>
---
 arch/x86/include/asm/invpcid.h | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/x86/include/asm/invpcid.h b/arch/x86/include/asm/invpcid.h
index 989cfa8..734482a 100644
--- a/arch/x86/include/asm/invpcid.h
+++ b/arch/x86/include/asm/invpcid.h
@@ -12,12 +12,9 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr,
 	 * stale TLB entries and, especially if we're flushing global
 	 * mappings, we don't want the compiler to reorder any subsequent
 	 * memory accesses before the TLB flush.
-	 *
-	 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
-	 * invpcid (%rcx), %rax in long mode.
 	 */
-	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
-		      : : "m" (desc), "a" (type), "c" (&desc) : "memory");
+	asm volatile("invpcid %[desc], %[type]"
+		     :: [desc] "m" (desc), [type] "r" (type) : "memory");
 }
 
 #define INVPCID_TYPE_INDIV_ADDR		0

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