| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <0a01e65d-5169-d528-49bd-e37ff970c211@baylibre.com>
Date: Wed, 13 May 2020 16:17:56 +0200
From: Neil Armstrong <narmstrong@...libre.com>
To: Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
robh+dt@...nel.org, khilman@...libre.com,
linux-amlogic@...ts.infradead.org, devicetree@...r.kernel.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 3/4] soc: amlogic: meson-ee-pwrc: add support for
Meson8/Meson8b/Meson8m2
On 20/04/2020 22:26, Martin Blumenstingl wrote:
> This adds support for the power domains on Meson8/Meson8b/Meson8m2.
> Meson8 doesn't use any reset lines while Meson8b and Meson8m2 use the
> same set of reset lines (which is different from the newer SoCs).
> Add dedicated compatible strings for Meson8, Meson8b and Meson8m2 to
> support these differences.
>
> Notable differences between Meson8 and G12A are:
> - there is no HHI_VPU_MEM_PD_REG2 on the 32-bit SoCs
> - the Meson8b datasheet describes an "audio DSP memory" power domain
> which is used for the hardware audio decoder
> - the "amlogic,ao-sysctrl" only includes the power management related
> registers on the 32-bit SoCs, meaning the for example the
> AO_RTI_GEN_PWR_SLEEP0 register is at offset (0x2 << 2) rather than
> (0x3a << 2). As result of this (0x38 << 2) is subtracted from the
> register offsets, which is the start of the power management related
> registers.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
> ---
> drivers/soc/amlogic/meson-ee-pwrc.c | 72 +++++++++++++++++++++++++++--
> 1 file changed, 69 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
> index 3f0261d53ad9..b30868da456a 100644
> --- a/drivers/soc/amlogic/meson-ee-pwrc.c
> +++ b/drivers/soc/amlogic/meson-ee-pwrc.c
> @@ -14,6 +14,7 @@
> #include <linux/reset-controller.h>
> #include <linux/reset.h>
> #include <linux/clk.h>
> +#include <dt-bindings/power/meson8-power.h>
> #include <dt-bindings/power/meson-g12a-power.h>
> #include <dt-bindings/power/meson-sm1-power.h>
>
> @@ -22,6 +23,12 @@
> #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
> #define AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
>
> +/*
> + * Meson8/Meson8b/Meson8m2 only expose the power management registers of
> + * the AO-bus as syscon. Above register offsets need to subtract this offset.
> + */
> +#define AO_RTI_GEN_MESON8_PMU_OFFSET (0x38 << 2)
This is weird, I would directly add the MESON8 PWR_SLEEP0 offset directly.
> +
> /* HHI Offsets */
>
> #define HHI_MEM_PD_REG0 (0x40 << 2)
> @@ -73,6 +80,13 @@ static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
> .iso_mask = BIT(9),
> };
>
> +static struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = {
> + .sleep_reg = AO_RTI_GEN_PWR_SLEEP0 - AO_RTI_GEN_MESON8_PMU_OFFSET,
> + .sleep_mask = BIT(8),
> + .iso_reg = AO_RTI_GEN_PWR_SLEEP0 - AO_RTI_GEN_MESON8_PMU_OFFSET,
> + .iso_mask = BIT(9),
> +};
> +
> #define SM1_EE_PD(__bit) \
> { \
> .sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \
> @@ -124,10 +138,20 @@ static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
> VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
> };
>
> -static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
> +static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_eth[] = {
> { HHI_MEM_PD_REG0, GENMASK(3, 2) },
> };
I would rename it meson_pwrc... since it's the same on all SoCs.
>
> +static struct meson_ee_pwrc_mem_domain meson8_pwrc_audio_dsp_mem[] = {
> + { HHI_MEM_PD_REG0, GENMASK(1, 0) },
> +};
> +
> +static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_vpu[] = {
> + VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
> + VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
> + VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
> +};
> +
> static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
> VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
> VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
> @@ -201,7 +225,27 @@ static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain);
> static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
> [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
> pwrc_ee_get_power, 11, 2),
> - [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
> + [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson8_pwrc_mem_eth),
> +};
> +
> +static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = {
> + [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
> + meson8_pwrc_mem_vpu, pwrc_ee_get_power,
> + 0, 1),
> + [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
> + meson8_pwrc_mem_eth),
> + [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
> + meson8_pwrc_audio_dsp_mem),
> +};
> +
> +static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = {
> + [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
> + meson8_pwrc_mem_vpu, pwrc_ee_get_power,
> + 11, 1),
> + [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
> + meson8_pwrc_mem_eth),
> + [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
> + meson8_pwrc_audio_dsp_mem),
> };
>
> static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
> @@ -216,7 +260,7 @@ static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
> [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
> pwrc_ee_get_power),
> [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
> - [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
> + [PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson8_pwrc_mem_eth),
> };
>
> struct meson_ee_pwrc_domain {
> @@ -470,12 +514,34 @@ static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
> .domains = g12a_pwrc_domains,
> };
>
> +static struct meson_ee_pwrc_domain_data meson_ee_m8_pwrc_data = {
> + .count = ARRAY_SIZE(meson8_pwrc_domains),
> + .domains = meson8_pwrc_domains,
> +};
> +
> +static struct meson_ee_pwrc_domain_data meson_ee_m8b_pwrc_data = {
> + .count = ARRAY_SIZE(meson8b_pwrc_domains),
> + .domains = meson8b_pwrc_domains,
> +};
> +
> static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
> .count = ARRAY_SIZE(sm1_pwrc_domains),
> .domains = sm1_pwrc_domains,
> };
>
> static const struct of_device_id meson_ee_pwrc_match_table[] = {
> + {
> + .compatible = "amlogic,meson8-pwrc",
> + .data = &meson_ee_m8_pwrc_data,
> + },
> + {
> + .compatible = "amlogic,meson8b-pwrc",
> + .data = &meson_ee_m8b_pwrc_data,
> + },
> + {
> + .compatible = "amlogic,meson8m2-pwrc",
> + .data = &meson_ee_m8b_pwrc_data,
> + },
> {
> .compatible = "amlogic,meson-g12a-pwrc",
> .data = &meson_ee_g12a_pwrc_data,
>
With these fixed:
Reviewed-by: Neil Armstrong <narmstrong@...libre.com>
Powered by blists - more mailing lists