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Message-ID: <d2e3741e-ba06-7578-b5f3-2af75e1e33c7@ti.com>
Date: Wed, 13 May 2020 12:16:03 -0500
From: Dan Murphy <dmurphy@...com>
To: Mark Brown <broonie@...nel.org>
CC: <lgirdwood@...il.com>, <perex@...ex.cz>, <tiwai@...e.com>,
<alsa-devel@...a-project.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ASoC: tlv320adcx140: Add controls for PDM clk and edge
Mark
On 5/13/20 10:32 AM, Mark Brown wrote:
> On Wed, May 13, 2020 at 09:47:46AM -0500, Dan Murphy wrote:
>
>> +static const char * const pdmclk_text[] = {
>> + "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
>> +};
>> +
>> +static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
>> + pdmclk_text);
>> +
>> +static const struct snd_kcontrol_new pdmclk_div_controls[] = {
>> + SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
>> +};
>> +
>> +static const char * const pdm_edge_text[] = {
>> + "Negative", "Positive"
>> +};
> Are these (especially the clock and polarity) things that are going to
> vary at runtime? I'd have expected these to come from the hardware
> rather than being something that could usefully change.
Some microphone support low power modes that use a slower clock.
Polarity will probably not change at run-time, but clock speed can
change to move mics from low power/low-resolution to higher
power/high-resolution mode.
So polarity can be made hardware specific but clocks should be configurable.
I can break these out into separate patches if you want.
Dan
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