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Message-ID: <20200513115655.s2i65tfy5m4skl35@mobilestation>
Date:   Wed, 13 May 2020 14:56:55 +0300
From:   Serge Semin <Sergey.Semin@...kalelectronics.ru>
To:     Mark Brown <broonie@...nel.org>
CC:     Serge Semin <fancer.lancer@...il.com>,
        Georgy Vlasov <Georgy.Vlasov@...kalelectronics.ru>,
        Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Arnd Bergmann <arnd@...db.de>,
        Allison Randal <allison@...utok.net>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Gareth Williams <gareth.williams.jx@...esas.com>,
        Rob Herring <robh+dt@...nel.org>, <linux-mips@...r.kernel.org>,
        <devicetree@...r.kernel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        <linux-spi@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 08/17] spi: dw: Clear DMAC register when done or stopped

On Fri, May 08, 2020 at 06:31:34PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 04:29:33PM +0300, Serge Semin wrote:
> > If DMAC register is left uncleared any further DMAless transfers
> > may cause the DMAC hardware handshaking interface getting activated.
> > So the next DMA-based Rx/Tx transaction will be started right
> > after the dma_async_issue_pending() method is invoked even if no
> > DMATDLR/DMARDLR conditions are met. This at the same time may cause
> > the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
> > must clear DMAC register after a current DMA-based transaction is
> > finished.
> 
> This also looks like a bugfix so should be pulled forwards to the start
> of the series if possible.

Ok.

-Sergey

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