lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 14 May 2020 18:27:46 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Ashok Raj <ashok.raj@...el.com>
Cc:     linux-pci@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH] pci: Fixes MaxPayloadSize (MPS) programming for RCiEP
 devices.

On Fri, Mar 27, 2020 at 02:16:15PM -0700, Ashok Raj wrote:
> Root Complex Integrated devices (RCiEP) do not have a Root Port before the
> device. pci_configure_mps() should simply stick the max value for MaxPayload
> size in Device Control, and for MaxReadReq. Unless pcie=pcie_bus-peer2peer
> is used in kernel commandline PCIE_BUS_PEER2PEER.
> 
> When MPS is configured lower, it could result in reduced performance.
> 
> Fixes: 9dae3a97297f ("PCI: Move MPS configuration check to pci_configure_device()")
> Signed-off-by: Ashok Raj <ashok.raj@...el.com>
> Tested-by: Dave Jiang <dave.jiang@...el.com>
> To: Bjorn Helgaas <bhelgaas@...gle.com>
> To: linux-pci@...r.kernel.org
> Cc: linux-kernel@...r.kernel.org
> Cc: stable@...r.kernel.org
> Cc: Ashok Raj <ashok.raj@...el.com>

Applied to pci/enumeration for v5.8, thanks!

> ---
>  drivers/pci/probe.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index eeff8a07..a738b1c 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1895,13 +1895,34 @@ static void pci_configure_mps(struct pci_dev *dev)
>  	struct pci_dev *bridge = pci_upstream_bridge(dev);
>  	int mps, mpss, p_mps, rc;
>  
> -	if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
> +	if (!pci_is_pcie(dev))
>  		return;
>  
>  	/* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
>  	if (dev->is_virtfn)
>  		return;
>  
> +	/*
> +	 * If this is a Root Complex Integrated Endpoint
> +	 * Simply program the max value from DEVCAP. No additional
> +	 * Lookup is necessary
> +	 */
> +	if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
> +		if (pcie_bus_config == PCIE_BUS_PEER2PEER)
> +			mps = 128;
> +		else
> +			mps = 128 << dev->pcie_mpss;
> +		rc = pcie_set_mps(dev, mps);
> +		if (rc) {
> +			pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
> +			 mps);
> +			return;
> +		}
> +	}
> +
> +	if (!bridge || !pci_is_pcie(bridge))
> +		return;
> +
>  	mps = pcie_get_mps(dev);
>  	p_mps = pcie_get_mps(bridge);
>  
> -- 
> 2.7.4
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ