linux-kernel - Re: [PATCH] MIPS: update tlb even if pte entry has no change

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Message-ID: <f165deac-1a71-dd88-dfe5-c1701f31567b@cogentembedded.com>
Date:   Thu, 14 May 2020 12:37:27 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:     Bibo Mao <maobibo@...ngson.cn>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Paul Burton <paulburton@...nel.org>,
        Dmitry Korotin <dkorotin@...ecomp.com>,
        Philippe Mathieu-Daudé <f4bug@...at.org>,
        Stafford Horne <shorne@...il.com>,
        Steven Price <steven.price@....com>,
        Anshuman Khandual <anshuman.khandual@....com>,
        Mike Rapoport <rppt@...ux.ibm.com>
Cc:     linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] MIPS: update tlb even if pte entry has no change

On 14.05.2020 12:35, Sergei Shtylyov wrote:

>> From: bibo mao <maobibo@...ngson.cn>
>>
>> If there are two threads reading the same memory and tlb miss happens,
>> one thread fills pte entry, the other reads new pte value during page fault
>> handling. PTE value may be updated before page faul, so the process need
> 
>     Fault.

    And "needs".

>> need update tlb still.

    Oh, and one "need" is enough. :-)

>> Also this patch define flush_tlb_fix_spurious_fault as empty, since it not
>> necessary to flush the page for all CPUs
>>
>> Signed-off-by: Bibo Mao <maobibo@...ngson.cn>
> [...]

MBR, Sergei