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Date: Fri, 15 May 2020 15:12:14 +0200 From: Guido Günther <agx@...xcpu.org> To: Laurent Pinchart <Laurent.pinchart@...asonboard.com>, David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>, Rob Herring <robh+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>, Pengutronix Kernel Team <kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>, NXP Linux Team <linux-imx@....com>, Andrzej Hajda <a.hajda@...sung.com>, Sam Ravnborg <sam@...nborg.org>, Anson Huang <Anson.Huang@....com>, Leonard Crestez <leonard.crestez@....com>, Lucas Stach <l.stach@...gutronix.de>, Peng Fan <peng.fan@....com>, Robert Chiras <robert.chiras@....com>, dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Subject: [RFC PATCH 5/6] arm64: dts: imx8mq: Add NWL dsi controller Add a node for the Northwestlogic MIPI DSI IP core, "disabled" by default. Signed-off-by: Guido Günther <agx@...xcpu.org> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0142f06ead12..6bbbf44e6be0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -889,6 +889,37 @@ sec_jr2: jr@...0 { }; }; + mipi_dsi: mipi-dsi@...00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30a00000 0x300>; + clocks = <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, + <&clk IMX8MQ_SYS1_PLL_266M>; + assigned-clock-rates = <80000000>, + <266000000>, + <20000000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, + <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; + reset-names = "byte", "dpi", "esc", "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&pgc_mipi>; + status = "disabled"; + }; + dphy: dphy@...00300 { compatible = "fsl,imx8mq-mipi-dphy"; reg = <0x30a00300 0x100>; -- 2.26.1
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