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Message-ID: <87a729dylz.fsf@nanos.tec.linutronix.de>
Date: Fri, 15 May 2020 17:08:56 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Steven Rostedt <rostedt@...dmis.org>
Cc: LKML <linux-kernel@...r.kernel.org>, x86@...nel.org,
"Paul E. McKenney" <paulmck@...nel.org>,
Andy Lutomirski <luto@...nel.org>,
Alexandre Chartre <alexandre.chartre@...cle.com>,
Frederic Weisbecker <frederic@...nel.org>,
Paolo Bonzini <pbonzini@...hat.com>,
Sean Christopherson <sean.j.christopherson@...el.com>,
Masami Hiramatsu <mhiramat@...nel.org>,
Petr Mladek <pmladek@...e.com>,
Joel Fernandes <joel@...lfernandes.org>,
Boris Ostrovsky <boris.ostrovsky@...cle.com>,
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Brian Gerst <brgerst@...il.com>,
Mathieu Desnoyers <mathieu.desnoyers@...icios.com>,
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"Peter Zijlstra \(Intel\)" <peterz@...radead.org>
Subject: Re: [patch V5 04/38] x86: Make hardware latency tracing explicit
Steven Rostedt <rostedt@...dmis.org> writes:
> On Tue, 12 May 2020 23:01:03 +0200
> Thomas Gleixner <tglx@...utronix.de> wrote:
>
>> --- a/arch/x86/kernel/cpu/mce/core.c
>> +++ b/arch/x86/kernel/cpu/mce/core.c
>> @@ -1916,7 +1916,7 @@ static __always_inline void exc_machine_
>> mce_check_crashing_cpu())
>> return;
>>
>> - nmi_enter();
>> + nmi_enter_notrace();
>
> Now a machine check exception could happen and be a cause of latency
> (although there may be more issues if it does). The "nmi_enter trace"
> version does two things. One is for time measurements (if available),
> and the other is just letting the hardware latency know it happen (a
> simple increment).
>
> The only thing that is checked is "smp_processor_id()" (I just
> remembered it doesn't need per cpu, as it only runs on a single CPU at
> a time).
>
> Could the notrace version supply the increment, and leave the
> trace_clock() in the trace version?
Yes, I can split it up that way.
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