linux-kernel - [PATCH v7 0/3] Optionally flush L1D cache on context switch

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Message-ID: <20200516103430.26527-1-sblbir@amazon.com>
Date:   Sat, 16 May 2020 20:34:27 +1000
From:   Balbir Singh <sblbir@...zon.com>
To:     <tglx@...utronix.de>, <linux-kernel@...r.kernel.org>
CC:     <jpoimboe@...hat.com>, <tony.luck@...el.com>,
        <keescook@...omium.org>, <benh@...nel.crashing.org>,
        <x86@...nel.org>, <dave.hansen@...el.com>,
        <thomas.lendacky@....com>, Balbir Singh <sblbir@...zon.com>
Subject: [PATCH v7 0/3] Optionally flush L1D cache on context switch

These are the remaining patches built on top of
https://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git/log/?h=x86/mm

for the series posted at
https://lore.kernel.org/lkml/20200510014803.12190-1-sblbir@amazon.com/

Changelog v7
- Split patch 5 from the previous series into two patches
- Reuse the prctl PR_GET/SET_SPECULATION_CTRL with PR_SPEC_L1D_FLUSH_OUT
    as the ctrl parameter
- Add the BUILD_BUG_ON that went missing that checks the placement of
    TIF_SPEC_L1D_FLUSH
- Update the documentation to reflect the changes

Balbir Singh (3):
  x86/mm: Optionally flush L1D on context switch
  prctl: Hook L1D flushing in via prctl
  Documentation: Add L1D flushing Documentation

 Documentation/admin-guide/hw-vuln/index.rst   |  1 +
 .../admin-guide/hw-vuln/l1d_flush.rst         | 51 +++++++++++++++++++
 Documentation/userspace-api/spec_ctrl.rst     |  7 +++
 arch/x86/include/asm/thread_info.h            |  9 +++-
 arch/x86/kernel/cpu/bugs.c                    | 28 ++++++++++
 arch/x86/mm/tlb.c                             | 39 ++++++++++++--
 include/uapi/linux/prctl.h                    |  1 +
 7 files changed, 131 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/admin-guide/hw-vuln/l1d_flush.rst

-- 
2.17.1