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Date:   Sun, 17 May 2020 15:32:26 +0530
From:   Taniya Das <tdas@...eaurora.org>
To:     Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>
Cc:     David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Andy Gross <agross@...nel.org>, devicetree@...r.kernel.org,
        robh@...nel.org, robh+dt@...nel.org
Subject: Re: [PATCH v1 3/3] clk: qcom: gcc: Add support for Secure control
 source clock

Hello Stephen,

Thanks for your review.

On 3/16/2020 11:19 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2020-03-16 03:54:42)
>> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
>> index ad75847..3302f19 100644
>> --- a/drivers/clk/qcom/gcc-sc7180.c
>> +++ b/drivers/clk/qcom/gcc-sc7180.c
>> @@ -817,6 +817,26 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
>>          },
>>   };
>>
>> +static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
>> +       F(4800000, P_BI_TCXO, 4, 0, 0),
>> +       F(19200000, P_BI_TCXO, 1, 0, 0),
>> +       { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
>> +       .cmd_rcgr = 0x3d030,
>> +       .mnd_width = 0,
>> +       .hid_width = 5,
>> +       .parent_map = gcc_parent_map_3,
>> +       .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
>> +       .clkr.hw.init = &(struct clk_init_data){
>> +               .name = "gcc_sec_ctrl_clk_src",
>> +               .parent_data = gcc_parent_data_3,
>> +               .num_parents = 3,
> 
> ARRAY_SIZE please.
> 

Will take care of the same.

>> +               .ops = &clk_rcg2_ops,
>> +       },
>> +};
>> +
>>   static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>>          .halt_reg = 0x82024,
>>          .halt_check = BRANCH_HALT_DELAY,

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

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