Message-ID: <CANr2M19unLW8n0P2DiOYEZ=GZcaD-L2ygPht_5HNtNZ6e4h6xQ@mail.gmail.com>
Date:   Mon, 18 May 2020 14:26:00 +0800
From:   Lecopzer Chen <lecopzer@...il.com>
To:     Sumit Garg <sumit.garg@...aro.org>
Cc:     julien.thierry.kdev@...il.com,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Mark Rutland <mark.rutland@....com>,
        Jian-Lin Chen <lecopzer.chen@...iatek.com>,
        alexander.shishkin@...ux.intel.com,
        Catalin Marinas <catalin.marinas@....com>, jolsa@...hat.com,
        acme@...nel.org, Peter Zijlstra <peterz@...radead.org>,
        mingo@...hat.com, linux-mediatek@...ts.infradead.org,
        matthias.bgg@...il.com, namhyung@...nel.org,
        Will Deacon <will@...nel.org>, yj.chiang@...iatek.com,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 0/3] arm64: perf: Add support for Perf NMI interrupts

HI Sumit,

Thanks for your information.

I've already implemented IPI (same as you did [1], little difference
in detail), hardlockup detector and perf in last year(2019) for
debuggability.
And now we tend to upstream to reduce kernel maintaining effort.
I'm glad if someone in ARM can do this work :)

Hi Julien,

Does any Arm maintainers can proceed this action?
This is really useful in debugging.
Thank you!!



[1] https://lkml.org/lkml/2020/4/24/328


Lecopzer

Sumit Garg <sumit.garg@...aro.org> 於 2020年5月18日 週一 下午1:46寫道：
>
> + Julien
>
> Hi Lecopzer,
>
> On Sat, 16 May 2020 at 18:20, Lecopzer Chen <lecopzer@...il.com> wrote:
> >
> > These series implement Perf NMI funxtionality and depends on
> > Pseudo NMI [1] which has been upstreamed.
> >
> > In arm64 with GICv3, Pseudo NMI was implemented for NMI-like interruts.
> > That can be extended to Perf NMI which is the prerequisite for hard-lockup
> > detector which had already a standard interface inside Linux.
> >
> > Thus the first step we need to implement perf NMI interface and make sure
> > it works fine.
> >
>
> This is something that is already implemented via Julien's patch-set
> [1]. Its v4 has been floating since July, 2019 and I couldn't find any
> major blocking comments but not sure why things haven't progressed
> further.
>
> Maybe Julien or Arm maintainers can provide updates on existing
> patch-set [1] and how we should proceed further with this interesting
> feature.
>
> And regarding hard-lockup detection, I have been able to enable it
> based on perf NMI events using Julien's perf patch-set [1]. Have a
> look at the patch here [2].
>
> [1] https://patchwork.kernel.org/cover/11047407/
> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2020-May/732227.html
>
> -Sumit
>
> > Perf NMI has been test by dd if=/dev/urandom of=/dev/null like the link [2]
> > did.
> >
> > [1] https://lkml.org/lkml/2019/1/31/535
> > [2] https://www.linaro.org/blog/debugging-arm-kernels-using-nmifiq
> >
> >
> > Lecopzer Chen (3):
> >   arm_pmu: Add support for perf NMI interrupts registration
> >   arm64: perf: Support NMI context for perf event ISR
> >   arm64: Kconfig: Add support for the Perf NMI
> >
> >  arch/arm64/Kconfig             | 10 +++++++
> >  arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++------
> >  drivers/perf/arm_pmu.c         | 51 ++++++++++++++++++++++++++++++----
> >  include/linux/perf/arm_pmu.h   |  6 ++++
> >  4 files changed, 88 insertions(+), 15 deletions(-)
> >
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@...ts.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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