linux-kernel - RE: [PATCH] dt-bindings: reset: Convert i.MX reset to json-schema

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Message-ID: <DB3PR0402MB3916154554C6AB2C6BBEDE1DF5B80@DB3PR0402MB3916.eurprd04.prod.outlook.com>
Date:   Mon, 18 May 2020 09:58:57 +0000
From:   Anson Huang <anson.huang@....com>
To:     Philipp Zabel <p.zabel@...gutronix.de>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH] dt-bindings: reset: Convert i.MX reset to json-schema

Hi, Philipp

> Subject: Re: [PATCH] dt-bindings: reset: Convert i.MX reset to json-schema
> 
> Hi Anson,
> 
> On Tue, 2020-05-12 at 10:23 +0800, Anson Huang wrote:
> > Convert the i.MX reset binding to DT schema format using json-schema.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@....com>
> 
> thank you for the conversion.
> 
> > ---
> >  .../devicetree/bindings/reset/fsl,imx-src.txt      | 49 ------------------
> >  .../devicetree/bindings/reset/fsl,imx-src.yaml     | 58
> ++++++++++++++++++++++
> >  2 files changed, 58 insertions(+), 49 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/reset/fsl,imx-src.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
> > b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
> > deleted file mode 100644
> > index 6ed79e6..0000000
> > --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
> > +++ /dev/null
> > @@ -1,49 +0,0 @@
> > -Freescale i.MX System Reset Controller
> > -======================================
> > -
> > -Please also refer to reset.txt in this directory for common reset
> > -controller binding usage.
> > -
> > -Required properties:
> > -- compatible: Should be "fsl,<chip>-src"
> > -- reg: should be register base and length as documented in the
> > -  datasheet
> > -- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
> > -  in this order.
> > -- #reset-cells: 1, see below
> > -
> > -example:
> > -
> > -src: src@...8000 {
> > -        compatible = "fsl,imx6q-src";
> > -        reg = <0x020d8000 0x4000>;
> > -        interrupts = <0 91 0x04 0 96 0x04>;
> > -        #reset-cells = <1>;
> > -};
> > -
> > -Specifying reset lines connected to IP modules
> > -==============================================
> > -
> > -The system reset controller can be used to reset the GPU, VPU, -IPU,
> > and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device -nodes
> > should specify the reset line on the SRC in their resets -property,
> > containing a phandle to the SRC device node and a -RESET_INDEX
> > specifying which module to reset, as described in -reset.txt
> > -
> > -example:
> > -
> > -        ipu1: ipu@...0000 {
> > -                resets = <&src 2>;
> > -        };
> > -        ipu2: ipu@...0000 {
> > -                resets = <&src 4>;
> > -        };
> > -
> > -The following RESET_INDEX values are valid for i.MX5:
> > -GPU_RESET     0
> > -VPU_RESET     1
> > -IPU1_RESET    2
> > -OPEN_VG_RESET 3
> > -The following additional RESET_INDEX value is valid for i.MX6:
> > -IPU2_RESET    4
> > diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> > b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> > new file mode 100644
> > index 0000000..276a533
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Freset%2Ffsl%2Cimx-src.yaml%23&amp;data=02%
> 7C01
> >
> +%7Canson.huang%40nxp.com%7Cd622f3b31cca4b2e7b4808d7fb0fae99%7C
> 686ea1d
> >
> +3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637253917082767416&amp;s
> data=7e%2
> >
> +FAy3dz4goXW6rNH2tAl3z5oNQ%2FIZ6Nykn4uBZ7S20%3D&amp;reserved=0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=02%7C01%7Cans
> on.hua
> >
> +ng%40nxp.com%7Cd622f3b31cca4b2e7b4808d7fb0fae99%7C686ea1d3bc2b
> 4c6fa92
> >
> +cd99c5c301635%7C0%7C0%7C637253917082767416&amp;sdata=U%2Fs60
> QKHaPc5Ar
> > +GxJP97FLL%2BsClgZkuSmeQWKofm4oQ%3D&amp;reserved=0
> > +
> > +title: Freescale i.MX System Reset Controller
> > +
> > +maintainers:
> > +  - Philipp Zabel <p.zabel@...gutronix.de>
> > +
> > +description: |
> > +  The system reset controller can be used to reset the GPU, VPU,
> > +  IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
> > +  nodes should specify the reset line on the SRC in their resets
> > +  property, containing a phandle to the SRC device node and a
> > +  RESET_INDEX specifying which module to reset, as described in
> > +  reset.txt
> > +
> > +  The following RESET_INDEX values are valid for i.MX5:
> > +    GPU_RESET     0
> > +    VPU_RESET     1
> > +    IPU1_RESET    2
> > +    OPEN_VG_RESET 3
> > +  The following additional RESET_INDEX value is valid for i.MX6:
> > +    IPU2_RESET    4
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: "fsl,imx51-src"
> 
> "fsl,imx51-src" is the only compatible the driver matches on, but we have
> these combinations on compatible SRCs in the device trees:
> 
>   "fsl,imx50-src", "fsl,imx51-src"
>   "fsl,imx51-src"
>   "fsl,imx53-src", "fsl,imx51-src"
>   "fsl,imx6q-src", "fsl,imx51-src"
>   "fsl,imx6sl-src", "fsl,imx51-src"
>   "fsl,imx6sll-src", "fsl,imx51-src"
>   "fsl,imx6sx-src", "fsl,imx51-src"
>   "fsl,imx6ul-src", "fsl,imx51-src"
> 
> That could be described using oneOf and and an items list of const values per
> SoC like in the qcom bindings.

Yes, I noticed this and will add all of them in V2 per SoC, thanks.

Anson