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Message-ID: <20200518110343.GY1634618@smile.fi.intel.com>
Date:   Mon, 18 May 2020 14:03:43 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Serge Semin <fancer.lancer@...il.com>,
        Mark Brown <broonie@...nel.org>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Arnd Bergmann <arnd@...db.de>,
        Allison Randal <allison@...utok.net>,
        Gareth Williams <gareth.williams.jx@...esas.com>,
        Rob Herring <robh+dt@...nel.org>, linux-mips@...r.kernel.org,
        devicetree@...r.kernel.org,
        Georgy Vlasov <Georgy.Vlasov@...kalelectronics.ru>,
        Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
        Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@...el.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Clement Leger <cleger@...ray.eu>, linux-spi@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 10/19] spi: dw: Use DMA max burst to set the request
 thresholds

On Sat, May 16, 2020 at 11:01:33PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 05:38:42PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 01:47:49PM +0300, Serge Semin wrote:
> > > Each channel of DMA controller may have a limited length of burst
> > > transaction (number of IO operations performed at ones in a single
> > > DMA client request). This parameter can be used to setup the most
> > > optimal DMA Tx/Rx data level values. In order to avoid the Tx buffer
> > > overrun we can set the DMA Tx level to be of FIFO depth minus the
> > > maximum burst transactions length. To prevent the Rx buffer underflow
> > > the DMA Rx level should be set to the maximum burst transactions length.
> > > This commit setups the DMA channels and the DW SPI DMA Tx/Rx levels
> > > in accordance with these rules.

...

> > >  	/* DMA info */
> > >  	struct dma_chan		*txchan;
> > > +	u32			txburst;
> > >  	struct dma_chan		*rxchan;
> > > +	u32			rxburst;
> > 
> > Leave u32 together, it may be optimal on 64-bit architectures where ABIs require padding.
> 
> It's not like anyone cared about padding in this structure in the first place)

I think I have been caring (to some extend).

> Though if v3 is required I'll group these members together.

>From what I see v3 is what Mark and me are waiting for. Mark, are we on the
same page here?

-- 
With Best Regards,
Andy Shevchenko


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