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Message-ID: <20200518115547.GC1957@C02TD0UTHF1T.local>
Date: Mon, 18 May 2020 12:55:47 +0100
From: Mark Rutland <mark.rutland@....com>
To: Will Deacon <will@...nel.org>
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Sami Tolvanen <samitolvanen@...gle.com>,
Kees Cook <keescook@...omium.org>,
Catalin Marinas <catalin.marinas@....com>,
Mark Rutland <mark.rutland@...com>,
Jann Horn <jannh@...gle.com>, Ard Biesheuvel <ardb@...nel.org>,
Peter Zijlstra <peterz@...radead.org>, kernel-team@...roid.com
Subject: Re: [PATCH 3/6] arm64: scs: Use 'scs_sp' register alias for x18
On Fri, May 15, 2020 at 06:27:53PM +0100, Will Deacon wrote:
> x18 holds the SCS stack pointer value, so introduce a register alias to
> make this easier to read in assembly code.
>
> Signed-off-by: Will Deacon <will@...nel.org>
I scanned through arm64 for all instances of x18, and it looks like
you've covered all the relevant uses here. In kvm we save/restore x18 a
bunch becasue it might be a platform register, but we do that
unconditionally and without knowledge of what it contains, so I think
that's fine to leave as-is. Therefore:
Reviewed-by: Mark Rutland <mark.rutland@....com>
As an aside, the comment in entry-ftrace.S is now stale where it says
that x18 is safe to clobber. I can send a patch to clean that up, unless
you want to do that yourself.
Mark.
> ---
> arch/arm64/include/asm/scs.h | 6 ++++--
> arch/arm64/kernel/entry.S | 10 +++++-----
> arch/arm64/kernel/head.S | 2 +-
> 3 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/include/asm/scs.h b/arch/arm64/include/asm/scs.h
> index 6b8cf4352fe3..d46efdd2060a 100644
> --- a/arch/arm64/include/asm/scs.h
> +++ b/arch/arm64/include/asm/scs.h
> @@ -7,12 +7,14 @@
> #include <asm/asm-offsets.h>
>
> #ifdef CONFIG_SHADOW_CALL_STACK
> + scs_sp .req x18
> +
> .macro scs_load tsk, tmp
> - ldr x18, [\tsk, #TSK_TI_SCS_SP]
> + ldr scs_sp, [\tsk, #TSK_TI_SCS_SP]
> .endm
>
> .macro scs_save tsk, tmp
> - str x18, [\tsk, #TSK_TI_SCS_SP]
> + str scs_sp, [\tsk, #TSK_TI_SCS_SP]
> .endm
> #else
> .macro scs_load tsk, tmp
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index cb0516e6f963..741faf0706f1 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -394,7 +394,7 @@ alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
> .macro irq_stack_entry
> mov x19, sp // preserve the original sp
> #ifdef CONFIG_SHADOW_CALL_STACK
> - mov x24, x18 // preserve the original shadow stack
> + mov x24, scs_sp // preserve the original shadow stack
> #endif
>
> /*
> @@ -416,7 +416,7 @@ alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
>
> #ifdef CONFIG_SHADOW_CALL_STACK
> /* also switch to the irq shadow stack */
> - adr_this_cpu x18, irq_shadow_call_stack, x26
> + adr_this_cpu scs_sp, irq_shadow_call_stack, x26
> #endif
>
> 9998:
> @@ -430,7 +430,7 @@ alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
> .macro irq_stack_exit
> mov sp, x19
> #ifdef CONFIG_SHADOW_CALL_STACK
> - mov x18, x24
> + mov scs_sp, x24
> #endif
> .endm
>
> @@ -1071,9 +1071,9 @@ SYM_CODE_START(__sdei_asm_handler)
> #ifdef CONFIG_SHADOW_CALL_STACK
> /* Use a separate shadow call stack for normal and critical events */
> cbnz w4, 3f
> - adr_this_cpu dst=x18, sym=sdei_shadow_call_stack_normal, tmp=x6
> + adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6
> b 4f
> -3: adr_this_cpu dst=x18, sym=sdei_shadow_call_stack_critical, tmp=x6
> +3: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6
> 4:
> #endif
>
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index 2b01c19c5483..1293baddfd20 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -426,7 +426,7 @@ SYM_FUNC_START_LOCAL(__primary_switched)
> mov x29, sp
>
> #ifdef CONFIG_SHADOW_CALL_STACK
> - adr_l x18, init_shadow_call_stack // Set shadow call stack
> + adr_l scs_sp, init_shadow_call_stack // Set shadow call stack
> #endif
>
> str_l x21, __fdt_pointer, x5 // Save FDT pointer
> --
> 2.26.2.761.g0e0b3e54be-goog
>
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