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Message-ID: <CAPcyv4hE6iW3MwW=qybN8aXN4wHJ7R2OCDCUEw9FdKu4NeZ6iw@mail.gmail.com>
Date: Mon, 18 May 2020 10:20:23 -0700
From: Dan Williams <dan.j.williams@...el.com>
To: David Woodhouse <dwmw2@...radead.org>
Cc: "hch@....de" <hch@....de>,
"david.e.box@...ux.intel.com" <david.e.box@...ux.intel.com>,
"linux-nvme@...ts.infradead.org" <linux-nvme@...ts.infradead.org>,
"sagi@...mberg.me" <sagi@...mberg.me>,
"lenb@...nel.org" <lenb@...nel.org>,
"rjw@...ysocki.net" <rjw@...ysocki.net>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"axboe@...com" <axboe@...com>,
"kbusch@...nel.org" <kbusch@...nel.org>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>
Subject: Re: [PATCH 0/2] Add support for StorageD3Enable _DSD property
On Mon, May 18, 2020 at 6:52 AM David Woodhouse <dwmw2@...radead.org> wrote:
>
> On Wed, 2020-04-29 at 05:20 +0000, Williams, Dan J wrote:
> > The *patch* is not trying to overrule NVME, and the best I can say is
> > that the Intel Linux team was not in the loop when this was being
> > decided between the platform BIOS implemenation and whomever thought
> > they could just publish random ACPI properties that impacted NVME
> > operation [1].
> >
> > So now David is trying to get these platform unbroken because they are
> > already shipping with this b0rkage.
>
> This is what we have WARN_TAINT() for though, right? It can suitably
> warn users when such breakage is detected in the platform.
>
I see WARN_TAINT() as "BIOS implemented its specification wrong". This
case is BIOS "implemented a mechanism in the wrong specification".
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