linux-kernel - Re: [PATCH V4 09/17] arm64/cpufeature: Add remaining feature bits in ID

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Date:   Tue, 19 May 2020 11:56:53 +0100
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     anshuman.khandual@....com, linux-arm-kernel@...ts.infradead.org
Cc:     catalin.marinas@....com, will@...nel.org, maz@...nel.org,
        mark.rutland@....com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V4 09/17] arm64/cpufeature: Add remaining feature bits in
 ID_AA64ISAR0 register

On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
> Enable TLB features bit in ID_AA64ISAR0 register as per ARM DDI 0487F.a
> specification.
> 
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will@...nel.org>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: Suzuki K Poulose <suzuki.poulose@....com>
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> 
> Suggested-by: Will Deacon <will@...nel.org>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>
> ---
>   arch/arm64/include/asm/sysreg.h | 1 +
>   arch/arm64/kernel/cpufeature.c  | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 0a0cbb3add89..ea075cc08c8f 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -601,6 +601,7 @@
>   
>   /* id_aa64isar0 */
>   #define ID_AA64ISAR0_RNDR_SHIFT		60
> +#define ID_AA64ISAR0_TLB_SHIFT		56
>   #define ID_AA64ISAR0_TS_SHIFT		52
>   #define ID_AA64ISAR0_FHM_SHIFT		48
>   #define ID_AA64ISAR0_DP_SHIFT		44
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 92186c40b817..ed0c400155c9 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -179,6 +179,7 @@ static bool __system_matches_cap(unsigned int n);
>    */
>   static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
>   	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
>   	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
>   	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
>   	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
> 

Heads up, this might conflict with other series which adds support for 
the TLBI range.

As such :

Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>