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Date: Thu, 21 May 2020 00:13:09 +0300 From: Serge Semin <Sergey.Semin@...kalelectronics.ru> To: Thomas Bogendoerfer <tsbogend@...ha.franken.de> CC: Serge Semin <fancer.lancer@...il.com>, Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>, Paul Burton <paulburton@...nel.org>, Ralf Baechle <ralf@...ux-mips.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Arnd Bergmann <arnd@...db.de>, Rob Herring <robh+dt@...nel.org>, <linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>, Vincenzo Frascino <vincenzo.frascino@....com>, Thomas Gleixner <tglx@...utronix.de>, <linux-mips@...r.kernel.org>, <linux-kernel@...r.kernel.org> Subject: Re: [PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled On Wed, May 20, 2020 at 08:40:24PM +0200, Thomas Bogendoerfer wrote: > On Wed, May 20, 2020 at 02:59:26PM +0300, Serge Semin wrote: > > I think there is a misunderstanding here. In this patch I am not enabling > > you are right, I've missed the fact, that this also needs to be enabled > in TLB entries. Strange that MIPS added the enable bit while R10k simply > do uncached acclerated, whenever TLB entry selects it. > > > If there is no misunderstanding and you said what you said, that even enabling > > the feature for utilization might be dangerous, let's at least leave the > > MIPS_CONF_MM, MIPS_CONF_MM_FULL and MIPS_CONF_MM_SYS_SYSAD fields > > definition in the "arch/mips/include/asm/mipsregs.h" header. I'll use > > them to enable the write-merge in my platform code. > > > > What do you think? > > I withdraw my concerns and will apply the patch as is. Great! Thanks. -Sergey > > Thomas. > > -- > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a > good idea. [ RFC1925, 2.3 ]
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