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Message-ID: <11ad0061-f0b3-a0ed-a216-f77eb45bcda1@gmail.com>
Date: Wed, 20 May 2020 12:51:17 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: Stephen Boyd <sboyd@...nel.org>,
Enric Balletbo i Serra <enric.balletbo@...labora.com>,
ck.hu@...iatek.com, mark.rutland@....com,
ulrich.hecht+renesas@...il.com
Cc: linux-kernel@...r.kernel.org, drinkcat@...omium.org,
hsinyi@...omium.org, Collabora Kernel ML <kernel@...labora.com>,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
Matthias Brugger <mbrugger@...e.com>, matthias.bgg@...nel.org,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Allison Randal <allison@...utok.net>,
Kate Stewart <kstewart@...uxfoundation.org>,
Michael Turquette <mturquette@...libre.com>,
Richard Fontana <rfontana@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH v2 3/4] clk / soc: mediatek: Bind clock and gpu driver for
mt2701
On 20/05/2020 12:13, Stephen Boyd wrote:
> Quoting Enric Balletbo i Serra (2020-04-01 13:17:35)
>> Now that the mmsys driver is the top-level entry point for the
>> multimedia subsystem, we could bind the clock and the gpu driver on
>> those devices that is expected to work, so the drm driver is
>> intantiated by the mmsys driver and display, hopefully, working again.
>>
>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
>> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@...nel.org>
>> ---
>
> Acked-by: Stephen Boyd <sboyd@...nel.org>
>
Now queued for v5.7-next/soc
Thanks!
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