Date:   Thu, 21 May 2020 08:57:10 -0600
From:   Rob Herring <robh@...nel.org>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Serge Semin <fancer.lancer@...il.com>,
        Mark Brown <broonie@...nel.org>,
        Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        John Garry <john.garry@...wei.com>,
        Chuanhong Guo <gch981213@...il.com>,
        Tomer Maimon <tmaimon77@...il.com>,
        Lee Jones <lee.jones@...aro.org>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        Arnd Bergmann <arnd@...db.de>,
        "open list:MIPS" <linux-mips@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>,
        devicetree@...r.kernel.org,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: spi: Add Baikal-T1 System Boot SPI
 Controller binding

On Mon, May 18, 2020 at 3:27 PM Serge Semin
<Sergey.Semin@...kalelectronics.ru> wrote:
>
> On Mon, May 18, 2020 at 09:26:59AM -0600, Rob Herring wrote:
> > On Fri, May 08, 2020 at 12:36:20PM +0300, Serge Semin wrote:
> > > Baikal-T1 Boot SPI is a part of the SoC System Controller and is
> > > responsible for the system bootup from an external SPI flash. It's a DW
> > > APB SSI-based SPI-controller with no interrupts, no DMA, with just one
> > > native chip-select available and a single reference clock. Since Baikal-T1
> > > SoC is normally booted up from an external SPI flash this SPI controller
> > > in most of the cases is supposed to be connected to a single SPI-nor
> > > flash. Additionally in order to provide a transparent from CPU point of
> > > view initial code execution procedure the system designers created an IP
> > > block which physically maps the SPI flash found at CS0 to a memory region.
> > >
> > > Co-developed-by: Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>
> > > Signed-off-by: Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>
> > > Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
> > > Cc: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
> > > Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
> > > Cc: Paul Burton <paulburton@...nel.org>
> > > Cc: Ralf Baechle <ralf@...ux-mips.org>
> > > Cc: John Garry <john.garry@...wei.com>
> > > Cc: Chuanhong Guo <gch981213@...il.com>
> > > Cc: Tomer Maimon <tmaimon77@...il.com>
> > > Cc: Lee Jones <lee.jones@...aro.org>
> > > Cc: Miquel Raynal <miquel.raynal@...tlin.com>
> > > Cc: Arnd Bergmann <arnd@...db.de>
> > > Cc: linux-mips@...r.kernel.org
> > > Cc: linux-spi@...r.kernel.org
> > > ---
> > >  .../bindings/spi/baikal,bt1-sys-ssi.yaml      | 100 ++++++++++++++++++
> > >  1 file changed, 100 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml b/Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml
> > > new file mode 100644
> > > index 000000000000..d9d3257d78f4
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/spi/baikal,bt1-sys-ssi.yaml
> > > @@ -0,0 +1,100 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/spi/baikal,bt1-sys-ssi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Baikal-T1 System Boot SSI Controller
> > > +
> > > +description: |
> > > +  Baikal-T1 System Controller includes a Boot SPI Controller, which is
> > > +  responsible for loading chip bootup code from an external SPI flash. In order
> > > +  to do this transparently from CPU point of view there is a dedicated IP block
> > > +  mapping the 16MB flash to a dedicated MMIO range. The controller is based on
> > > +  the DW APB SSI IP-core but equipped with very limited resources: no IRQ,
> > > +  no DMA, a single native CS being necessarily connected to a 16MB SPI flash
> > > +  (otherwise the system won't bootup from the flash), internal Tx/Rx FIFO of
> > > +  just 8 bytes depth. Access to DW APB SSI controller registers is mutually
> > > +  exclusive from normal MMIO interface and from physically mapped SPI Flash
> > > +  memory. So either one or another way of using the controller functionality
> > > +  can be enabled at a time.
> > > +
> > > +maintainers:
> > > +  - Serge Semin <fancer.lancer@...il.com>
> > > +
> > > +allOf:
> > > +  - $ref: spi-controller.yaml#
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: baikal,bt1-sys-ssi
> > > +
> > > +  reg:
> > > +    items:
> > > +      - description: Baikal-T1 Boot Controller configuration registers
> > > +      - description: Physically mapped SPI flash ROM found at CS0
> > > +
> > > +  reg-names:
> > > +    items:
> > > +      - const: config
> > > +      - const: map
> > > +
> > > +  clocks:
> > > +    description: SPI Controller reference clock source
> >
> > Can drop this.
>
> Ok.
>
> >
> > > +    maxItems: 1
> > > +
> > > +  clock-names:
> > > +    items:
> > > +      - const: ssi_clk
> > > +
> > > +  num-cs:
> > > +    const: 1
> > > +
> > > +patternProperties:
> > > +  "^.*@[0-9a-f]+":
> > > +    type: object
> > > +    properties:
> > > +      reg:
> > > +        minimum: 0
> > > +        maximum: 0
> > > +
> > > +      spi-rx-bus-width:
> > > +        const: 1
> > > +
> > > +      spi-tx-bus-width:
> > > +        const: 1
> >
> > What's the point of these 2 properties if they aren't required?
>
> Yes, they are optional, but this is a constraint on the bus-width parameters.
> DW APB SSI provides a single laned Tx and Rx.

Are you just trying to keep someone from saying 'spi-tx-bus-width: 2'
for example?

You could also say 'spi-tx-bus-width: false' here to disallow the
property. I guess the above is fine.

Rob

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