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Date:   Fri, 22 May 2020 14:13:40 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Mark Brown <broonie@...nel.org>,
        Linus Walleij <linus.walleij@...ricsson.com>,
        Vinod Koul <vkoul@...nel.org>, Feng Tang <feng.tang@...el.com>,
        Grant Likely <grant.likely@...retlab.ca>,
        Alan Cox <alan@...ux.intel.com>,
        Serge Semin <fancer.lancer@...il.com>,
        Georgy Vlasov <Georgy.Vlasov@...kalelectronics.ru>,
        Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Arnd Bergmann <arnd@...db.de>,
        Rob Herring <robh+dt@...nel.org>, linux-mips@...r.kernel.org,
        devicetree@...r.kernel.org,
        Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
        "wuxu.wu" <wuxu.wu@...wei.com>, Clement Leger <cleger@...ray.eu>,
        Linus Walleij <linus.walleij@...aro.org>,
        linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 01/16] spi: dw: Add Tx/Rx finish wait methods to the
 MID DMA

On Fri, May 22, 2020 at 03:07:50AM +0300, Serge Semin wrote:
> Since DMA transfers are performed asynchronously with actual SPI
> transaction, then even if DMA transfers are finished it doesn't mean
> all data is actually pushed to the SPI bus. Some data might still be
> in the controller FIFO. This is specifically true for Tx-only
> transfers. In this case if the next SPI transfer is recharged while
> a tail of the previous one is still in FIFO, we'll loose that tail
> data. In order to fix this lets add the wait procedure of the Tx/Rx
> SPI transfers completion after the corresponding DMA transactions
> are finished.

...

> Fixes: 7063c0d942a1 ("spi/dw_spi: add DMA support")

Usually we put this before any other tags.

> Cc: Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
> Cc: Paul Burton <paulburton@...nel.org>
> Cc: Ralf Baechle <ralf@...ux-mips.org>
> Cc: Arnd Bergmann <arnd@...db.de>
> Cc: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>

> Cc: Rob Herring <robh+dt@...nel.org>

Are you sure Rob needs this to see?
You really need to shrink Cc lists of the patches to send them on common sense basis.

> Cc: linux-mips@...r.kernel.org

> Cc: devicetree@...r.kernel.org

Ditto.

...

> Changelog v4:
> - Get back ndelay() method to wait for an SPI transfer completion.
>   spi_delay_exec() isn't suitable for the atomic context.

OTOH we may teach spi_delay_exec() to perform atomic sleeps.

...

> +	while (dw_spi_dma_tx_busy(dws) && retry--)
> +		ndelay(ns);

I might be mistaken, but I think I told that this one misses to keep power
management in mind.

Have you read Documentation/process/volatile-considered-harmful.rst ?

...

> +	while (dw_spi_dma_rx_busy(dws) && retry--)
> +		ndelay(ns);

Ditto.

-- 
With Best Regards,
Andy Shevchenko


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