lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ccf86d21-2ecf-7873-1c30-fbea880b9081@nvidia.com>
Date:   Sat, 23 May 2020 14:33:12 -0700
From:   John Hubbard <jhubbard@...dia.com>
To:     Moritz Fischer <mdf@...nel.org>
CC:     LKML <linux-kernel@...r.kernel.org>, Xu Yilun <yilun.xu@...el.com>,
        Wu Hao <hao.wu@...el.com>, <linux-fpga@...r.kernel.org>
Subject: Re: [PATCH v2] fpga: dfl: afu: convert get_user_pages() -->
 pin_user_pages()

On 2020-05-23 13:57, Moritz Fischer wrote:
> On Fri, May 22, 2020 at 06:52:34PM -0700, John Hubbard wrote:
>> On 2020-05-19 13:14, John Hubbard wrote:
>>> This code was using get_user_pages_fast(), in a "Case 2" scenario
>>> (DMA/RDMA), using the categorization from [1]. That means that it's
>>> time to convert the get_user_pages_fast() + put_page() calls to
>>> pin_user_pages_fast() + unpin_user_pages() calls.
>>>
>>> There is some helpful background in [2]: basically, this is a small
>>> part of fixing a long-standing disconnect between pinning pages, and
>>> file systems' use of those pages.
>>>
>>> [1] Documentation/core-api/pin_user_pages.rst
>>>
>>> [2] "Explicit pinning of user-space pages":
>>>       https://lwn.net/Articles/807108/
>>>
>>> Cc: Xu Yilun <yilun.xu@...el.com>
>>> Cc: Wu Hao <hao.wu@...el.com>
>>> Cc: Moritz Fischer <mdf@...nel.org>
>>> Cc: linux-fpga@...r.kernel.org
>>> Signed-off-by: John Hubbard <jhubbard@...dia.com>
>>
>>
>> Hi Moritz and FPGA developers,
>>
>> Is this OK? And if so, is it going into your git tree? Or should I
>> send it up through a different tree? (I'm new to the FPGA development
>> model).
> 
> I can take it, sorry for sluggish response.
> 

That's great news, thanks Moritz! Sorry to be pushy, just didn't want it
to get lost. :)

thanks,
-- 
John Hubbard
NVIDIA

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ