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Date:   Sun, 24 May 2020 22:17:58 +0200
From:   Boris Brezillon <boris.brezillon@...labora.com>
To:     Pratyush Yadav <p.yadav@...com>
Cc:     Tudor Ambarus <tudor.ambarus@...rochip.com>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        Richard Weinberger <richard@....at>,
        Vignesh Raghavendra <vigneshr@...com>,
        Mark Brown <broonie@...nel.org>,
        Nicolas Ferre <nicolas.ferre@...rochip.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Ludovic Desroches <ludovic.desroches@...rochip.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Michal Simek <michal.simek@...inx.com>,
        <linux-mtd@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <linux-spi@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>, Sekhar Nori <nsekhar@...com>,
        Mason Yang <masonccyang@...c.com.tw>
Subject: Re: [PATCH v8 02/19] spi: spi-mem: allow specifying a command's
 extension

On Sat, 23 May 2020 04:10:25 +0530
Pratyush Yadav <p.yadav@...com> wrote:

> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 69491f3a515d..4e4292f0ee1d 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
>  	int nio = 1, i, ret;
>  	u32 ss_ctrl;
>  	u8 addr[8];
> +	u8 opcode = op->cmd.opcode & 0xff;

You don't need the '& 0xff' here, the cast to an u8 will truncate the
value anyway.

>  
>  	ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
>  	if (ret)
> @@ -393,7 +394,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
>  	writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
>  	       mxic->regs + HC_CFG);
>  
> -	ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1);
> +	ret = mxic_spi_data_xfer(mxic, &opcode, NULL, 1);
>  	if (ret)
>  		goto out;
>  
> diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
> index 17641157354d..41389856e14a 100644
> --- a/drivers/spi/spi-zynq-qspi.c
> +++ b/drivers/spi/spi-zynq-qspi.c
> @@ -527,20 +527,21 @@ static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
>  	struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master);
>  	int err = 0, i;
>  	u8 *tmpbuf;
> +	u8 opcode = op->cmd.opcode & 0xff;
>  

Ditto.

>  	dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
> -		op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
> +		opcode, op->cmd.buswidth, op->addr.buswidth,
>  		op->dummy.buswidth, op->data.buswidth);
>  
>  	zynq_qspi_chipselect(mem->spi, true);
>  	zynq_qspi_config_op(xqspi, mem->spi);
>  
> -	if (op->cmd.opcode) {
> +	if (opcode) {

Unrelated to this patch, but this test is wrong. I don't see why we
couldn't have a '0' opcode. The test should be dropped or done on the
new op->cmd.nbytes field.

>  		reinit_completion(&xqspi->data_completion);
> -		xqspi->txbuf = (u8 *)&op->cmd.opcode;
> +		xqspi->txbuf = &opcode;
>  		xqspi->rxbuf = NULL;
> -		xqspi->tx_bytes = sizeof(op->cmd.opcode);
> -		xqspi->rx_bytes = sizeof(op->cmd.opcode);
> +		xqspi->tx_bytes = op->cmd.nbytes;
> +		xqspi->rx_bytes = op->cmd.nbytes;
>  		zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
>  		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
>  				ZYNQ_QSPI_IXR_RXTX_MASK);

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