linux-kernel - [PATCH v3 2/6] arm64: Add level-hinted TLB invalidation helper

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Message-ID: <20200525125300.794-3-yezhenyu2@huawei.com>
Date:   Mon, 25 May 2020 20:52:56 +0800
From:   Zhenyu Ye <yezhenyu2@...wei.com>
To:     <catalin.marinas@....com>, <peterz@...radead.org>,
        <mark.rutland@....com>, <will@...nel.org>,
        <aneesh.kumar@...ux.ibm.com>, <akpm@...ux-foundation.org>,
        <npiggin@...il.com>, <arnd@...db.de>, <rostedt@...dmis.org>,
        <maz@...nel.org>, <suzuki.poulose@....com>, <tglx@...utronix.de>,
        <yuzhao@...gle.com>, <Dave.Martin@....com>, <steven.price@....com>,
        <broonie@...nel.org>, <guohanjun@...wei.com>
CC:     <yezhenyu2@...wei.com>, <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-arch@...r.kernel.org>,
        <linux-mm@...ck.org>, <arm@...nel.org>, <xiexiangyou@...wei.com>,
        <prime.zeng@...ilicon.com>, <zhangshaokun@...ilicon.com>,
        <kuhn.chenqun@...wei.com>
Subject: [PATCH v3 2/6] arm64: Add level-hinted TLB invalidation helper

From: Marc Zyngier <maz@...nel.org>

Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.

Signed-off-by: Marc Zyngier <maz@...nel.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@...wei.com>
Reviewed-by: Catalin Marinas <catalin.marinas@....com>
---
 arch/arm64/include/asm/tlbflush.h | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index bc3949064725..8adbd6fd8489 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -10,6 +10,7 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/bitfield.h>
 #include <linux/mm_types.h>
 #include <linux/sched.h>
 #include <asm/cputype.h>
@@ -59,6 +60,34 @@
 		__ta;						\
 	})
 
+#define TLBI_TTL_MASK	GENMASK_ULL(47, 44)
+
+#define __tlbi_level(op, addr, level) do {			\
+	u64 arg = addr;						\
+								\
+	if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) &&	\
+	    level) {						\
+		u64 ttl = level;				\
+								\
+		switch (PAGE_SIZE) {				\
+		case SZ_4K:					\
+			ttl |= 1 << 2;				\
+			break;					\
+		case SZ_16K:					\
+			ttl |= 2 << 2;				\
+			break;					\
+		case SZ_64K:					\
+			ttl |= 3 << 2;				\
+			break;					\
+		}						\
+								\
+		arg &= ~TLBI_TTL_MASK;				\
+		arg |= FIELD_PREP(TLBI_TTL_MASK, ttl);		\
+	}							\
+								\
+	__tlbi(op,  arg);					\
+} while (0)
+
 /*
  *	TLB Invalidation
  *	================
-- 
2.19.1