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Message-ID: <159056850384.88029.10852284922297394339@swboyd.mtv.corp.google.com>
Date:   Wed, 27 May 2020 01:35:03 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     airlied@...ux.ie, alexandre.torgue@...com,
        andy.shevchenko@...il.com, broonie@...nel.org, daniel@...ll.ch,
        dillon.minfei@...il.com, linus.walleij@...aro.org,
        mcoquelin.stm32@...il.com, mturquette@...libre.com,
        noralf@...nnes.org, p.zabel@...gutronix.de, robh+dt@...nel.org,
        sam@...nborg.org, thierry.reding@...il.com
Cc:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org,
        linux-stm32@...md-mailman.stormreply.com,
        dri-devel@...ts.freedesktop.org, linux-clk@...r.kernel.org,
        dillonhua@...il.com, dillon min <dillon.minfei@...il.com>
Subject: Re: [PATCH v6 5/9] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate

Quoting dillon.minfei@...il.com (2020-05-27 00:27:29)
> From: dillon min <dillon.minfei@...il.com>
> 
> This is due to misuse \u2018PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c
> 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in
> include/dt-bindings/clock/stm32fx-clock.h).
> 
> 'post_div' point to 'post_div_data[]', 'post_div->pll_num'
> is PLL_I2S or PLL_SAI.
> 
> 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return
> from stm32f4_rcc_register_pll() but, at line 1777 of
> driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]',
> equal to 'clks[PLL_SAI]', this is invalid array member at that time.
> 
> Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
> Signed-off-by: dillon min <dillon.minfei@...il.com>
> ---

Acked-by: Stephen Boyd <sboyd@...nel.org>

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