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Message-ID: <20200529193130.GA2805164@bogus>
Date: Fri, 29 May 2020 13:31:30 -0600
From: Rob Herring <robh@...nel.org>
To: "Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@...ux.intel.com>
Cc: linux-kernel@...r.kernel.org, linux-mtd@...ts.infradead.org,
devicetree@...r.kernel.org, miquel.raynal@...tlin.com,
richard@....at, vigneshr@...com, arnd@...db.de,
brendanhiggins@...gle.com, tglx@...utronix.de,
boris.brezillon@...labora.com, anders.roxell@...aro.org,
masonccyang@...c.com.tw, linux-mips@...r.kernel.org,
hauke.mehrtens@...el.com, andriy.shevchenko@...el.com,
qi-ming.wu@...el.com, cheol.yong.kim@...el.com
Subject: Re: [PATCH v10 1/2] dt-bindings: mtd: Add Nand Flash Controller
support for Intel LGM SoC
On Thu, May 28, 2020 at 11:39:28PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@...ux.intel.com>
>
> Add YAML file for dt-bindings to support NAND Flash Controller
> on Intel's Lightning Mountain SoC.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@...ux.intel.com>
> ---
> .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 93 ++++++++++++++++++++++
> 1 file changed, 93 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
>
> diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
> new file mode 100644
> index 000000000000..afecc9920e04
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel LGM SoC NAND Controller Device Tree Bindings
> +
> +allOf:
> + - $ref: "nand-controller.yaml"
> +
> +maintainers:
> + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@...ux.intel.com>
> +
> +properties:
> + compatible:
> + const: intel,lgm-nand-controller
Doesn't match the example.
> +
> + reg:
> + maxItems: 6
> +
> + reg-names:
> + items:
> + - const: ebunand
> + - const: hsnand
> + - const: nand_cs0
> + - const: nand_cs1
> + - const: addr_sel0
> + - const: addr_sel1
> +
> + clocks:
> + maxItems: 1
> +
> + dmas:
> + maxItems: 2
> +
> + dma-names:
> + items:
> + - const: tx
> + - const: rx
> +
> +patternProperties:
> + "^nand@[a-f0-9]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 7
> +
> + nand-ecc-mode: true
> +
> + nand-ecc-algo:
> + const: hw
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - dmas
> + - dma-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + nand-controller@...00000 {
> + compatible = "intel,lgm-nand";
> + reg = <0xe0f00000 0x100>,
> + <0xe1000000 0x300>,
> + <0xe1400000 0x8000>,
> + <0xe1c00000 0x1000>,
> + <0x17400000 0x4>,
> + <0x17c00000 0x4>;
> + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
> + "addr_sel0", "addr_sel1";
> + clocks = <&cgu0 125>;
> + dmas = <&dma0 8>, <&dma0 9>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + nand@0 {
> + reg = <0>;
> + nand-on-flash-bbt;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> + };
> +
> +...
> --
> 2.11.0
>
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