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Message-ID: <159072495287.69627.17133221754230289904@swboyd.mtv.corp.google.com>
Date: Thu, 28 May 2020 21:02:32 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Adam Ford <aford173@...il.com>, Rob Herring <robh@...nel.org>
Cc: linux-clk <linux-clk@...r.kernel.org>,
Adam Ford-BE <aford@...conembedded.com>,
Charles Stevens <charles.stevens@...icpd.com>,
Michael Turquette <mturquette@...libre.com>,
Marek Vasut <marek.vasut@...il.com>,
devicetree <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2 2/3] clk: vc5: Enable addition output configurations of the Versaclock
Quoting Adam Ford (2020-05-12 15:21:49)
> On Tue, May 12, 2020 at 5:05 PM Rob Herring <robh@...nel.org> wrote:
> >
> > On Sat, May 02, 2020 at 07:21:25AM -0500, Adam Ford wrote:
> > > The existing driver is expecting the Versaclock to be pre-programmed,
> > > and only sets the output frequency. Unfortunately, not all devices
> > > are pre-programmed, and the Versaclock chip has more options beyond
> > > just the frequency.
> > >
> > > This patch enables the following additional features:
> > >
> > > - Programmable voltage: 1.8V, 2.5V, or 3.3V
> > > - Slew Percentage of normal: 85%, 90%, or 100%
> > > - Output Type: LVPECL, CMOS, HCSL, or LVDS
> > >
> > > Signed-off-by: Adam Ford <aford173@...il.com>
> >
> >
> > > diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clk/versaclock.h
> > > new file mode 100644
> > > index 000000000000..c6a6a0946564
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clk/versaclock.h
> >
> > Belongs in binding patch.
>
> I can do that, but the binding patch will have to be applied before
> the rest of the series, or the source won't build because it's
> referencing the bindings. Is that OK?
Yes that's usually how it works.
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