linux-kernel - Re: [PATCH v5 05/16] spi: dw: Add SPI Rx-done wait method to DMA-based transfer

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Date:   Fri, 29 May 2020 12:46:48 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc:     Mark Brown <broonie@...nel.org>,
        Grant Likely <grant.likely@...retlab.ca>,
        Linus Walleij <linus.walleij@...ricsson.com>,
        Feng Tang <feng.tang@...el.com>,
        Alan Cox <alan@...ux.intel.com>, Vinod Koul <vkoul@...nel.org>,
        Serge Semin <fancer.lancer@...il.com>,
        Georgy Vlasov <Georgy.Vlasov@...kalelectronics.ru>,
        Ramil Zaripov <Ramil.Zaripov@...kalelectronics.ru>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Arnd Bergmann <arnd@...db.de>,
        Rob Herring <robh+dt@...nel.org>, linux-mips@...r.kernel.org,
        devicetree@...r.kernel.org, linux-spi@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 05/16] spi: dw: Add SPI Rx-done wait method to
 DMA-based transfer

On Fri, May 29, 2020 at 06:59:03AM +0300, Serge Semin wrote:
> Having any data left in the Rx FIFO after the DMA engine claimed it has
> finished all DMA transactions is an abnormal situation, since the DW SPI
> controller driver expects to have all the data being fetched and placed
> into the SPI Rx buffer at that moment. In case if this has happened we
> assume that DMA engine still may be doing the data fetching, thus we give
> it sometime to finish. If after a short period of time the data is still
> left in the Rx FIFO, the driver will give up waiting and return an error
> indicating that the SPI controller/DMA engine must have hung up or failed
> at some point of doing their duties.

...

> +static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
> +{
> +	int retry = WAIT_RETRIES;
> +	struct spi_delay delay;
> +	unsigned long ns, us;
> +	u32 nents;
> +
> +	/*
> +	 * It's unlikely that DMA engine is still doing the data fetching, but
> +	 * if it's let's give it some reasonable time. The timeout calculation
> +	 * is based on the synchronous APB/SSI reference clock rate, on a
> +	 * number of data entries left in the Rx FIFO, times a number of clock
> +	 * periods normally needed for a single APB read/write transaction
> +	 * without PREADY signal utilized (which is true for the DW APB SSI
> +	 * controller).
> +	 */
> +	nents = dw_readl(dws, DW_SPI_RXFLR);

> +	ns = NSEC_PER_SEC / dws->max_freq * 4 * nents;

I think we may slightly increase precision by writing this like

	ns = 4 * NSEC_PER_SEC / dws->max_freq * nents;


> +	if (ns <= NSEC_PER_USEC) {
> +		delay.unit = SPI_DELAY_UNIT_NSECS;
> +		delay.value = ns;
> +	} else {
> +		us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
> +		delay.unit = SPI_DELAY_UNIT_USECS;
> +		delay.value = clamp_val(us, 0, USHRT_MAX);
> +	}
> +
> +	while (dw_spi_dma_rx_busy(dws) && retry--)
> +		spi_delay_exec(&delay, NULL);
> +
> +	if (retry < 0) {
> +		dev_err(&dws->master->dev, "Rx hanged up\n");
> +		return -EIO;
> +	}
> +
> +	return 0;
> +}

-- 
With Best Regards,
Andy Shevchenko