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Message-ID: <159083264246.17951.4135007103117136248.tip-bot2@tip-bot2>
Date: Sat, 30 May 2020 09:57:22 -0000
From: "tip-bot2 for Lai Jiangshan" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Lai Jiangshan <laijs@...ux.alibaba.com>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>,
Thomas Gleixner <tglx@...utronix.de>, x86 <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: [tip: x86/entry] x86/hw_breakpoint: Prevent data breakpoints on
per_cpu cpu_tss_rw
The following commit has been merged into the x86/entry branch of tip:
Commit-ID: 9a06f99a03a0f961047bbae4ee80ce9265757bfe
Gitweb: https://git.kernel.org/tip/9a06f99a03a0f961047bbae4ee80ce9265757bfe
Author: Lai Jiangshan <laijs@...ux.alibaba.com>
AuthorDate: Fri, 29 May 2020 23:27:31 +02:00
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Sat, 30 May 2020 10:00:06 +02:00
x86/hw_breakpoint: Prevent data breakpoints on per_cpu cpu_tss_rw
cpu_tss_rw is not directly referenced by hardware, but cpu_tss_rw is
accessed in CPU entry code, especially when #DB shifts its stacks.
If a data breakpoint would be set on cpu_tss_rw.x86_tss.ist[IST_INDEX_DB],
it would cause recursive #DB ending up in a double fault.
Add it to the list of protected items.
Signed-off-by: Lai Jiangshan <laijs@...ux.alibaba.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Link: https://lkml.kernel.org/r/20200526014221.2119-4-laijs@linux.alibaba.com
Link: https://lkml.kernel.org/r/20200529213320.897976479@infradead.org
---
arch/x86/kernel/hw_breakpoint.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index f859095..f311bbf 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -255,6 +255,15 @@ static inline bool within_cpu_entry(unsigned long addr, unsigned long end)
if (within_area(addr, end, (unsigned long)get_cpu_gdt_rw(cpu),
GDT_SIZE))
return true;
+
+ /*
+ * cpu_tss_rw is not directly referenced by hardware, but
+ * cpu_tss_rw is also used in CPU entry code,
+ */
+ if (within_area(addr, end,
+ (unsigned long)&per_cpu(cpu_tss_rw, cpu),
+ sizeof(struct tss_struct)))
+ return true;
}
return false;
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