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Message-ID: <20200601081746.GB28016@leoy-ThinkPad-X240s>
Date: Mon, 1 Jun 2020 16:17:46 +0800
From: Leo Yan <leo.yan@...aro.org>
To: Adrian Hunter <adrian.hunter@...el.com>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>,
Jiri Olsa <jolsa@...hat.com>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Will Deacon <will@...nel.org>,
James Clark <james.clark@....com>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Namhyung Kim <namhyung@...nel.org>,
Andi Kleen <ak@...ux.intel.com>,
Jin Yao <yao.jin@...ux.intel.com>,
Ian Rogers <irogers@...gle.com>,
Thomas Gleixner <tglx@...utronix.de>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Al Grant <al.grant@....com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Mike Leach <mike.leach@...aro.org>,
Tan Xiaojun <tanxiaojun@...wei.com>
Subject: Re: [PATCH v8 2/3] perf auxtrace: Add four itrace options
On Mon, Jun 01, 2020 at 10:24:00AM +0300, Adrian Hunter wrote:
> On 30/05/20 3:24 pm, Leo Yan wrote:
> > From: Tan Xiaojun <tanxiaojun@...wei.com>
> >
> > This patch is to add four options to synthesize events which are
> > described as below:
> >
> > 'f': synthesize first level cache events
> > 'm': synthesize last level cache events
> > 't': synthesize TLB events
> > 'a': synthesize remote access events
> >
> > This four options will be used by ARM SPE as their first consumer.
> >
> > Signed-off-by: Tan Xiaojun <tanxiaojun@...wei.com>
> > Signed-off-by: James Clark <james.clark@....com>
> > Signed-off-by: Leo Yan <leo.yan@...aro.org>
> > Tested-by: James Clark <james.clark@....com>
>
> Acked-by: Adrian Hunter <adrian.hunter@...el.com>
Thanks a lot for reviewing, Adrian.
Leo
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