linux-kernel - Re: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock

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Message-ID: <87h7vtq2ta.fsf@soft-dev15.microsemi.net>
Date:   Tue, 2 Jun 2020 10:39:29 +0200
From:   Lars Povlsen <lars.povlsen@...rochip.com>
To:     Rob Herring <robh@...nel.org>
CC:     Lars Povlsen <lars.povlsen@...rochip.com>,
        SoC Team <soc@...nel.org>, "Arnd Bergmann" <arnd@...db.de>,
        Stephen Boyd <sboyd@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Steen Hegelund <Steen.Hegelund@...rochip.com>,
        Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
        Olof Johansson <olof@...om.net>,
        Michael Turquette <mturquette@...libre.com>,
        <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <linux-gpio@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>
Subject: Re: [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock


Rob Herring writes:

> On Wed, May 13, 2020 at 02:55:28PM +0200, Lars Povlsen wrote:
>> This add the DT bindings documentation for the Sparx5 SoC DPLL clock
>>
>> Reviewed-by: Alexandre Belloni <alexandre.belloni@...tlin.com>
>> Signed-off-by: Lars Povlsen <lars.povlsen@...rochip.com>
>> ---
>>  .../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>> new file mode 100644
>> index 0000000000000..594007d8fc59a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microchip Sparx5 DPLL Clock
>> +
>> +maintainers:
>> +  - Lars Povlsen <lars.povlsen@...rochip.com>
>> +
>> +description: |
>> +  The Sparx5 DPLL clock controller generates and supplies clock to
>> +  various peripherals within the SoC.
>> +
>> +  This binding uses common clock bindings
>> +  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +
>> +properties:
>> +  compatible:
>> +    const: microchip,sparx5-dpll
>> +
>> +  reg:
>> +    items:
>> +      - description: dpll registers
>
> For a single entry, just:
>
> maxItems: 1

Ok.

>
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  # Clock provider for eMMC:
>> +  - |
>> +    clks: clks@...10000c {
>
> clock-controller@...0000c {
>

Got that.

>> +         compatible = "microchip,sparx5-dpll";
>> +         #clock-cells = <1>;
>> +         reg = <0x1110000c 0x24>;
>
> Looks like this is a sub-block in some other h/w block. What's the
> parent device? That should be described and this should be part of it
> either as a single node or a child node. Without a complete view of what
> this block has I can't provide any guidance.

No, as Alex noted to a similar comment in the temp. sensor driver, the
chip is using packed register spaces predominantly. So don't put too
much into the register offsets.

---Lars

>
> Rob

--
Lars Povlsen,
Microchip