linux-kernel - 回复：[PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU

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Date:   Wed, 03 Jun 2020 17:42:28 +0800
From:   "李扬韬" <frank@...winnertech.com>
To:     "Maxime Ripard" <maxime@...no.tech>
Cc:     "wens" <wens@...e.org>, "robh+dt" <robh+dt@...nel.org>,
        "mturquette" <mturquette@...libre.com>, "sboyd" <sboyd@...nel.org>,
        "linus.walleij" <linus.walleij@...aro.org>,
        "p.zabel" <p.zabel@...gutronix.de>,
        "黄烁生" <huangshuosheng@...winnertech.com>,
        "tiny.windzz" <tiny.windzz@...il.com>,
        "linux-arm-kernel" <linux-arm-kernel@...ts.infradead.org>,
        "devicetree" <devicetree@...r.kernel.org>,
        "linux-kernel" <linux-kernel@...r.kernel.org>,
        "linux-clk" <linux-clk@...r.kernel.org>,
        "linux-gpio" <linux-gpio@...r.kernel.org>
Subject: 回复：[PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU

>> + /* Enable the lock bits on all PLLs */
>> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
>> +  val = readl(reg + pll_regs[i]);
>> +  val |= BIT(29);
>
>Having a define for that would be nice here
>
>> +  writel(val, reg + pll_regs[i]);
>> + }
>> +
>> + /*
>> +  * In order to pass the EMI certification, the SDM function of
>> +  * the peripheral 1 bus is enabled, and the frequency is still
>> +  * calculated using the previous division factor.
>> +  */
>> + writel(0xd1303333, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG);
>
>Same here

Having a define? I don’t quite understand what you mean, 
can you give me an example?

MBR,
Yangtao