linux-kernel - Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps

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Message-ID: <66453e142fb3798b86159a5d473efabb@codeaurora.org>
Date:   Fri, 05 Jun 2020 19:45:03 +0530
From:   Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To:     Jonathan Marek <jonathan@...ek.ca>
Cc:     linux-arm-msm@...r.kernel.org, Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree-owner@...r.kernel.org
Subject: Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node

On 2020-05-25 15:07, Sai Prakash Ranjan wrote:
> Hi Jonathan,
> 
> On 2020-05-24 08:08, Jonathan Marek wrote:
>> Add the apps_smmu node for sm8150. Note that adding the iommus field 
>> for
>> UFS is required because initializing the iommu removes the bypass 
>> mapping
>> that created by the bootloader.
>> 
>> Signed-off-by: Jonathan Marek <jonathan@...ek.ca>
>> ---
>>  arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 
>> ++++++++++++++++++++++++++++
>>  1 file changed, 91 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> index a36512d1f6a1..acb839427b12 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@...4000 {
>>  			resets = <&gcc GCC_UFS_PHY_BCR>;
>>  			reset-names = "rst";
>> 
>> +			iommus = <&apps_smmu 0x300 0>;
>> +
>>  			clock-names =
>>  				"core_clk",
>>  				"bus_aggr_clk",
>> @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@...0000 {
>>  				compatible = "snps,dwc3";
>>  				reg = <0 0x0a600000 0 0xcd00>;
>>  				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> +				iommus = <&apps_smmu 0x140 0>;
>>  				snps,dis_u2_susphy_quirk;
>>  				snps,dis_enblslpm_quirk;
>>  				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>> @@ -742,6 +745,94 @@ spmi_bus: spmi@...0000 {
>>  			cell-index = <0>;
>>  		};
>> 
>> +		apps_smmu: iommu@...00000 {
>> +			compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
> 
> This should be qcom,sm8150-smmu-500 and also you need to update the 
> arm-smmu
> binding with this compatible in a separate patch.
> 

I tested out this series with my coresight patches for enabling SMMU 
translation
for ETR on SM8150, it works fine. With this above comment addressed and 
with
Bjorn's comments on commit description addressed,

Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>

Thanks,
Sai

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