linux-kernel - Re: [RFC PATCH] PCI: Remove End-End TLP as PASID dependency

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Date:   Wed, 10 Jun 2020 16:00:25 +0800
From:   Zhangfei Gao <zhangfei.gao@...aro.org>
To:     Jean-Philippe Brucker <jean-philippe@...aro.org>
Cc:     Bjorn Helgaas <bhelgaas@...gle.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Arnd Bergmann <arnd@...db.de>, kenneth-lee-2012@...mail.com,
        Wangzhou <wangzhou1@...ilicon.com>, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH] PCI: Remove End-End TLP as PASID dependency



On 2020/6/10 下午3:46, Jean-Philippe Brucker wrote:
> On Wed, Jun 10, 2020 at 12:18:14PM +0800, Zhangfei Gao wrote:
>> Some platform devices appear as PCI and have PCI cfg space,
>> but are actually on the AMBA bus.
>> They can support PASID via smmu stall feature, but does not
>> support tlp since they are not real pci devices.
>> So remove tlp as a PASID dependency.
>>
>> Signed-off-by: Zhangfei Gao <zhangfei.gao@...aro.org>
>> ---
>>   drivers/pci/ats.c | 3 ---
>>   1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
>> index 390e92f..8e31278 100644
>> --- a/drivers/pci/ats.c
>> +++ b/drivers/pci/ats.c
>> @@ -344,9 +344,6 @@ int pci_enable_pasid(struct pci_dev *pdev, int features)
>>   	if (WARN_ON(pdev->pasid_enabled))
>>   		return -EBUSY;
>>   
>> -	if (!pdev->eetlp_prefix_path)
>> -		return -EINVAL;
>> -
> This check is useful, and follows the PCI specification (4.0r1.0
> 2.2.10.2 End-End TLP Prefix Processing: "Software should ensure that TLPs
> containing End-End TLP Prefixes are not sent to components that do not
> support them.")
Thanks Jean,
>
> Why not set the eetlp_prefix_path bit from a PCI quirk?  Unlike the stall
> problem from the other thread, this one looks like a simple design mistake
> that can be fixed easily in future iterations of the platform: just set
> the "End-End TLP Prefix Supported" bit in the Device Capability 2 Register
> of all bridges.
Yes, we can still set eetlp_prefix_path bit from a PCI quirk.

And we also have considered adding this bit in Device Capability 2 
Register in future silicon.
But we hesitated that it does reflect the real function: from register, 
it can support tlp, but in fact, it does not.

Thanks