linux-kernel - [PATCH] clk: qoriq: add LS1021A core pll mux options

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Message-Id: <20200610113837.27117-1-matthias.schiffer@ew.tq-group.com>
Date:   Wed, 10 Jun 2020 13:38:37 +0200
From:   Matthias Schiffer <matthias.schiffer@...tq-group.com>
To:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>
Cc:     linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Michael Krummsdorf <michael.krummsdorf@...group.com>,
        Matthias Schiffer <matthias.schiffer@...tq-group.com>
Subject: [PATCH] clk: qoriq: add LS1021A core pll mux options

From: Michael Krummsdorf <michael.krummsdorf@...group.com>

This allows to clock the cores with 1 GHz, 500 MHz and 250 MHz.

Signed-off-by: Michael Krummsdorf <michael.krummsdorf@...group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@...tq-group.com>
---
 drivers/clk/clk-qoriq.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 374afcab89af..5942e9874bc0 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -244,6 +244,14 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
 	},
 };
 
+static const struct clockgen_muxinfo ls1021a_cmux = {
+	{
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
+	}
+};
+
 static const struct clockgen_muxinfo ls1028a_hwa1 = {
 	{
 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
@@ -577,7 +585,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
 	{
 		.compat = "fsl,ls1021a-clockgen",
 		.cmux_groups = {
-			&t1023_cmux
+			&ls1021a_cmux
 		},
 		.cmux_to_group = {
 			0, -1
-- 
2.17.1