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Message-ID: <8ef8c7c4-3560-274d-3043-ddf5b87e794a@codeaurora.org>
Date: Thu, 11 Jun 2020 17:48:58 +0530
From: Rajendra Nayak <rnayak@...eaurora.org>
To: Ravi Kumar Bokka <rbokka@...eaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Rob Herring <robh+dt@...nel.org>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
saiprakash.ranjan@...eaurora.org, dhavalp@...eaurora.org,
mturney@...eaurora.org, sparate@...eaurora.org,
c_rbokka@...eaurora.org, mkurumel@...eaurora.org
Subject: Re: [RFC v2 1/3] dt-bindings: nvmem: Add devicetree bindings for
qfprom-efuse
On 6/11/2020 3:18 PM, Ravi Kumar Bokka wrote:
> This patch adds dt-bindings document for qfprom-efuse controller.
there is an existing bindings doc (in .txt) which you should convert to yaml,
and then add another patch to extend it.
>
> Signed-off-by: Ravi Kumar Bokka <rbokka@...eaurora.org>
> ---
> .../devicetree/bindings/nvmem/qfprom.yaml | 52 ++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/qfprom.yaml
>
> diff --git a/Documentation/devicetree/bindings/nvmem/qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qfprom.yaml
> new file mode 100644
> index 0000000..7c8fc31
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/qfprom.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/nvmem/qfprom.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies Inc, QFPROM Efuse bindings
> +
> +maintainers:
> + - Ravi Kumar Bokka <rbokka@...eaurora.org>
> +
> +allOf:
> + - $ref: "nvmem.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qfprom
> +
> + reg:
> + maxItems: 3
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> +
> + qfprom@...000 {
> + compatible = "qcom,qfprom";
> + reg = <0 0x00780000 0 0x7a0>,
> + <0 0x00782000 0 0x100>,
> + <0 0x00784000 0 0x8ff>;
> + reg-names = "raw", "conf", "corrected";
> + clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
> + clock-names = "secclk";
> +
> + qusb2p_hstx_trim: hstx-trim-primary@25b {
> + reg = <0x25b 0x1>;
> + bits = <1 3>;
> + };
> + };
> +
> + &qfprom {
> + vcc-supply = <&vreg_l11a_1p8>;
> + };
> +
>
--
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