linux-kernel - [PATCH] cpufreq: intel_pstate: Add additional OOB enabling bit

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Message-Id: <20200611174838.2822533-1-srinivas.pandruvada@linux.intel.com>
Date:   Thu, 11 Jun 2020 10:48:38 -0700
From:   Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
To:     lenb@...nel.org, viresh.kumar@...aro.org, rjw@...ysocki.net
Cc:     linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
        Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
Subject: [PATCH] cpufreq: intel_pstate: Add additional OOB enabling bit

Add additional bit for OOB (Out of band) enabling of P-states. In this
case intel_pstate shouldn't load. Currently, only "BIT(8) == 1" of the
MSR MSR_MISC_PWR_MGMT is considered as OOB. Also add "BIT(18) == 1" as
OOB condition.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
---
 drivers/cpufreq/intel_pstate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 8e23a698ce04..f21761443c90 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -2686,8 +2686,8 @@ static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
 	id = x86_match_cpu(intel_pstate_cpu_oob_ids);
 	if (id) {
 		rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
-		if (misc_pwr & (1 << 8)) {
-			pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
+		if ((misc_pwr & BIT(8)) || (misc_pwr & BIT(18))) {
+			pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
 			return true;
 		}
 	}
-- 
2.24.1