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Message-Id: <20200611211144.9421-1-luca@lucaceresoli.net>
Date: Thu, 11 Jun 2020 23:11:40 +0200
From: Luca Ceresoli <luca@...aceresoli.net>
To: linux-fpga@...r.kernel.org
Cc: Luca Ceresoli <luca@...aceresoli.net>,
Moritz Fischer <mdf@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Michal Simek <michal.simek@...inx.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Anatolij Gustschin <agust@...x.de>
Subject: [PATCH 1/5] dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too
The Xilinx 7-series uses the same protocol, mention that.
Signed-off-by: Luca Ceresoli <luca@...aceresoli.net>
---
.../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
index cfa4ed42b62f..9f103f3872e8 100644
--- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
+++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
@@ -1,11 +1,14 @@
Xilinx Slave Serial SPI FPGA Manager
-Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
-what is referred to as "slave serial" interface.
+Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
+bitstream over what is referred to as "slave serial" interface.
The slave serial link is not technically SPI, and might require extra
circuits in order to play nicely with other SPI slaves on the same bus.
-See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+See:
+- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
Required properties:
- compatible: should contain "xlnx,fpga-slave-serial"
--
2.27.0
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